Altera cyclone V Technical Reference page 187

4-44
gpio_ext_porta
Bit
2
id
1
cd
0
ns
gpio_ext_porta
Reading this register reads the values of the GPIO inputs.
Module Instance
fpgamgrregs
Offset:
0x850
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
Altera Corporation
Name
Used by software to clear an INIT_DONE edge
interrupt.
Value
0x0
0x1
Used by software to clear an CONF_DONE edge
interrupt.
Value
0x0
0x1
Used by software to clear an nSTATUS edge interrupt.
Value
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
fpo cdp
RO RO
0x0 0x0
Description
Description
No interrupt clear
Clear interrupt
Description
No interrupt clear
Clear interrupt
Description
No interrupt clear
Clear interrupt
Base Address
0xFF706000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RO RO RO RO
0x0 0x0 0x0 0x0
Access
Register Address
0xFF706850
21 20 19 18
5 4 3 2
prr ccd crc id
RO RO RO RO
0x0 0x0 0x0 0x0
cv_5v4
2016.10.28
Reset
WO 0x0
WO 0x0
WO 0x0
17 16
1 0
cd ns
RO RO 0x0
0x0
FPGA Manager
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