Performance Monitoring Unit - Altera cyclone V Technical Reference

9-12
The FPGA Slaves Region
Related Information
L2 Cache
The FPGA Slaves Region
The Cortex-A9 MPU subsystem supports the variable-sized FPGA slaves region to communicate with
FPGA-based peripherals. This region can start as low as
settings. The top of the FPGA slaves region is located at
slaves region can range from 0 to
The HPS Peripherals Region
The HPS peripherals region is the top 64 MB in the address space, starting at
to
0xFFFFFFFF
Altera Cortex-A9 MPU subsystem.

Performance Monitoring Unit

Each Cortex-A9 processor has a Performance Monitoring Unit (PMU). The PMU supports 58 events to
gather statistics on the operation of the processor and memory system. Six counters in the PMU
accumulate the events in real time. The PMU counters are accessible either from the processor itself, using
the Coprocessor 14 (CP14) interface, or from an external debugger. The events are also supplied to the
PTM and can be used for trigger or trace.
Related Information
ARM Infocenter
For more information about the PMU, refer to the Performance Monitoring Unit chapter of the Cortex-A9
Technical Reference Manual, available on the ARM Infocenter website.
ARM Cortex-A9 MPCore Timers
There is one interval timer and one watchdog timer for each processor.
Functional Description
Each timer is private, meaning that only its associated processor can access it. If the watchdog timer is not
needed, it can be configured as a second interval timer.
Each private interval and watchdog timer has the following features:
• A 32-bit counter that optionally generates an interrupt when it reaches zero
• Configurable starting values for the counter
• An eight-bit prescaler value to qualify the clock period
Implementation Details
The timers are configurable to either single-shot or auto-reload mode. The timer blocks are clocked by
mpu_periph_clk
Altera Corporation
on page 9-61
0x3C000000
. The HPS peripherals region is always allocated to the HPS dedicated peripherals for the
running at ¼ the rate of the
, depending on the L2 cache filter
0xC0000000
. As a result, the size of the FPGA
0xFBFFFFFF
bytes.
.
mpu_clk
Cortex-A9 Microprocessor Unit Subsystem
2016.10.28
and extending
0xFC000000
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