Altera cyclone V Technical Reference page 45

2-8
Main Clock Group
Table 2-5: Main PLL Output Assignments
PLL
Main
The counter outputs from the main PLL can have their frequency further divided by programmable
dividers external to the PLL. Transitions to a different divide value occur on the fastest output clock, one
clock cycle prior to the slowest clock's rising edge. For example the clock transitions on cycle 15 of the
divide-by-16 divider for the main C2 output and cycle 3 of the divide-by-4 divider for the main C0 output.
The following figure shows how each counter output from the main PLL can have its frequency further
divided by programmable post-PLL dividers. Green-colored clock gating logic is directly controlled by
software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored
clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the
MPU subsystem clocks.
(7) The maximum frequency depends on the speed grade of the device.
Altera Corporation
Output Counter
C0
C1
C2
C3
C4
C5
Clock Name
osc1_clk
mpu_base_clk
(7)
osc1_clk
main_base_clk
(7)
osc1_clk
dbg_base_clk
base_clk
Up to 432 MHz
main_qspi_base_
clk
Up to 250 MHz for
main_nand_
the NAND flash
sdmmc_base_clk
controller and up to
200 MHz for the SD/
MMC controller
osc1_clk
cfg_h2f_user0_
125 MHz for driving
base_clk
configuration and
100 MHz for the user
clock
Frequency Phase Shift Control
to varies No
to varies No
/4 to No
mpu_
/2
No
No
to No
cv_5v4
2016.10.28
Clock Manager
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