Altera cyclone V Technical Reference page 874

cv_5v4
2016.10.28
ecc_enable
Enable controller ECC check bit generation and correction
Module Instance
nandregs
Offset:
0xE0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ecc_enable Fields
Bit
0
flag
global_int_enable
Global Interrupt enable and Error/Timeout disable.
Module Instance
nandregs
Offset:
0xF0
Access:
RW
NAND Flash Controller
Send Feedback
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Enables or disables controller ECC capabilities. When
enabled, controller calculates ECC check-bits and
writes them onto device on program operation. On
page reads, check-bits are recomputed and errors
reported, if any, after comparing with stored check-
bits. When disabled, controller does not compute
check-bits. [list][*]1 - ECC Enabled [*]0 - ECC
disabled[/list]
0xFFB80000
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
ecc_enable
Register Address
0xFFB800E0
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB800F0
13-53
17 16
1 0
flag
RW 0x1
Reset
RW 0x1
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