Table Of Contents - Altera cyclone V Technical Reference

TOC-2
Contents
Introduction to the Hard Processor System....................................................... 1-1
Features of the HPS......................................................................................................................................1-3
HPS Block Diagram and System Integration........................................................................................... 1-4
Endian Support.......................................................................................................................................... 1-15
Introduction to the Hard Processor System Address Map...................................................................1-15
Document Revision History.....................................................................................................................1-20
Clock Manager.....................................................................................................2-1
Features of the Clock Manager...................................................................................................................2-1
Clock Manager Block Diagram and System Integration........................................................................ 2-2
Functional Description of the Clock Manager.........................................................................................2-4
Clock Manager Address Map and Register Definitions........................................................................2-23
Document Revision History.....................................................................................................................2-73
Reset Manager..................................................................................................... 3-1
Reset Manager Block Diagram and System Integration......................................................................... 3-2
Functional Description of the Reset Manager....................................................................................... 3-10
Altera Corporation
HPS Block Diagram......................................................................................................................... 1-4
Cortex-A9 MPCore..........................................................................................................................1-5
HPS Interfaces.................................................................................................................................. 1-5
System Interconnect.........................................................................................................................1-6
On-Chip Memory............................................................................................................................ 1-7
Flash Memory Controllers.............................................................................................................. 1-8
Support Peripherals..........................................................................................................................1-9
Interface Peripherals...................................................................................................................... 1-11
CoreSight Debug and Trace..........................................................................................................1-14
HPS Address Spaces.......................................................................................................................1-15
HPS Peripheral Region Address Map..........................................................................................1-17
L4 Peripheral Clocks........................................................................................................................2-3
Clock Manager Building Blocks.....................................................................................................2-4
Hardware-Managed and Software-Managed Clocks...................................................................2-7
Clock Groups.................................................................................................................................... 2-7
Resets............................................................................................................................................... 2-17
Safe Mode........................................................................................................................................2-17
Interrupts.........................................................................................................................................2-18
Clock Usage By Module................................................................................................................ 2-18
Clock Manager Module Address Map.........................................................................................2-24
HPS External Reset Sources............................................................................................................3-3
Reset Controller................................................................................................................................3-4
Module Reset Signals....................................................................................................................... 3-5
Slave Interface and Status Register.............................................................................................. 3-10