System Interconnect - Altera cyclone V Technical Reference

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Other HPS Interfaces
Other HPS Interfaces
• TPIU trace—sends trace data created in the HPS to the FPGA fabric
• FPGA System Trace Macrocell (STM) —an interface that allows the FPGA fabric to send hardware
events to be stored in the HPS trace data
• FPGA cross–trigger—an interface that allows the CoreSight trigger system to send triggers to IP cores
in the FPGA, and vise versa
• DMA peripheral interface—multiple peripheral–request channels
• FPGA manager interface—signals that communicate with the FPGA fabric for boot and configuration
• Interrupts—allow soft IP cores to supply interrupts directly to the MPU interrupt controller
• MPU standby and events—signals that notify the FPGA fabric that the MPU is in standby mode and
signals that wake up Cortex–A9 processors from a wait for event (WFE) state
• HPS debug interface – an interface that allows the HPS debug control domain (debug APB) to extend
into FPGA
Other HPS–FPGA communications channels:
• FPGA clocks and resets
• HPS–to–FPGA JTAG—allows the HPS to master the FPGA JTAG chain

System Interconnect

The system interconnect consists of the main L3 interconnect and level 4 (L4) buses. The L3 interconnect
is an ARM NIC-301 module composed of the following switches:
• L3 main switch
• Connects the master, slaves, and other subswitches
• Provides 64-bit switching capabilities
• L3 master peripheral switch
• Connects master ports of peripherals with integrated DMA controllers to the L3 main switch
• L3 slave peripheral switch
• Connects slave ports of peripherals to the L3 main switch
Related Information
System Interconnect
SDRAM Controller Subsystem
HPS and FPGA fabric masters have access to the SDRAM controller subsystem.
The SDRAM controller subsystem implements the following high-level features:
• Support for double data rate 2 (DDR2), DDR3, and low-power double data rate 2 (LPDDR2) devices
• Error correction code (ECC) support, including calculation, single-bit error correction and write-back,
and error counters
• Fully-programmable timing parameter support for all JEDEC-specified timing parameters
• All ports support memory protection and mutual accesses
• FPGA fabric interface with up to six ports that can be combined for a data width up to 256-bits wide
using Avalon-MM and AXI interfaces.
The SDRAM controller subsystem is composed of the SDRAM controller, DDR PHY, control and status
registers and their associated interfaces.
Altera Corporation
on page 7-1
Introduction to the Hard Processor System
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2016.10.28