Altera cyclone V Technical Reference page 184

cv_5v4
2016.10.28
Bit
4
ccd
3
crc
2
id
1
cd
0
ns
gpio_porta_eoi
This register is written by software to clear edge interrupts generated by each individual GPIO input. This
register always reads back as zero.
FPGA Manager
Send Feedback
Name
Indicates whether CVP_CONF_DONE has an active
interrupt or not (before masking).
Value
0x0
0x1
Indicates whether CRC_ERROR has an active
interrupt or not (before masking).
Value
0x0
0x1
Indicates whether INIT_DONE has an active
interrupt or not (before masking).
Value
0x0
0x1
Indicates whether CONF_DONE has an active
interrupt or not (before masking).
Value
0x0
0x1
Indicates whether nSTATUS has an active interrupt
or not (before masking).
Value
0x0
0x1
Description
Description
Inactive
Active
Description
Inactive
Active
Description
Inactive
Active
Description
Inactive
Active
Description
Inactive
Active
4-41
gpio_porta_eoi
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
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