Acp Id Mapper Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Table 9-9: Page Decoder Values
0
1
2
3
With this page decode information, a master can read or write to any 1 GB region of the 4 GB memory
space while maintaining cache coherency with the MPU subsystem.
Using this feature, a debugger can have a coherent view into main memory, without having to stop the
processor. For example, at reset the DAP input ID (0x001) is mapped to output ID 2, so the debugger can
vary the 1 GB window that the DAP accesses without affecting any other traffic flow to the ACP.

ACP ID Mapper Address Map and Register Definitions

This section lists the ACP ID Mapper register address map and describes the registers.
ACP ID Mapper Registers Address Map
Registers in the ACP ID Mapper module
Base Address:
ACP ID Mapper Registers
Register
vid2rd on page 9-39
vid2wr on page 9-39
vid3rd on page 9-40
vid3wr on page 9-41
vid4rd on page 9-42
vid4wr on page 9-43
vid5rd on page 9-44
Cortex-A9 Microprocessor Unit Subsystem
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Page
0xFF707000
Offset Width Acces
0x0 32
0x4 32
0x8 32
0xC 32
0x10 32
0x14 32
0x18 32
ACP ID Mapper Address Map and Register Definitions
Address Range
0x00000000—0x3FFFFFFF
0x40000000—0x7FFFFFFF
0x80000000—0xBFFFFFFF
0xC0000000—0xFFFFFFFF
Reset Value
s
Read AXI Master Mapping
RW 0x80040010
Register for Fixed Virtual ID 2
Write AXI Master Mapping
RW 0x80040010
Register for Fixed Virtual ID 2
Read AXI Master Mapping
RW 0x0
Register for Fixed Virtual ID 3
Write AXI Master Mapping
RW 0x0
Register for Fixed Virtual ID 3
Read AXI Master Mapping
RW 0x0
Register for Fixed Virtual ID 4
Write AXI Master Mapping
RW 0x0
Register for Fixed Virtual ID 4
Read AXI Master Mapping
RW 0x0
Register for Fixed Virtual ID 5
9-37
Description
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