Hps Memory Interface Simulation - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
The EMIF parameter editor contains four additional tabs: PHY Settings, Memory Parameters, Memory
Timing, and Board Settings. The parameters available on these tabs are similar to those available in the
parameter editors for non-SoC device families.
There are significant differences between the EMIF parameter editor for the Hard Processor System and
the parameter editors for non-SoC devices, as follows:
• Because the HPS memory controller is not configurable through the software, the Controller and
Diagnostic tabs, which exist for non-SoC devices, are not present in the EMIF parameter editor for the
hard processor system.
• Unlike the protocol-specific parameter editors for non-SoC devices, the EMIF parameter editor for the
Hard Processor System supports multiple protocols, therefore there is an SDRAM Protocol parameter,
where you can specify your external memory interface protocol. By default, the EMIF parameter editor
assumes the DDR3 protocol, and other parameters are automatically populated with DDR3-
appropriate values. If you select a protocol other than DDR3, change other associated parameter values
appropriately.
• Unlike the memory interface clocks in the FPGA, the memory interface clocks for the HPS are initial‐
ized by the boot-up code using values provided by the configuration process. You may accept the values
provided by UniPHY, or you may use your own PLL settings. If you choose to specify your own PLL
settings, you must indicate that the clock frequency that UniPHY should use is the requested clock
frequency, and not the achieved clock frequency calculated by UniPHY.
Note: The HPS does not support EMIF synthesis generation, compilation, or timing analysis. The HPS
hard memory controller cannot be bonded with another hard memory controller on the FPGA
portion of the device.

HPS Memory Interface Simulation

Qsys provides a complete simulation model of the HPS memory interface controller and PHY, providing
cycle-level accuracy, comparable to the simulation models for the FPGA memory interface.
The simulation model supports only the skip-cal simulation mode; quick-cal and full-cal are not
supported. An example design is not provided. However, you can create a test design by adding the traffic
generator component to your design using Qsys. Also, the HPS simulation model does not use external
memory pins to connect to the DDR memory model; instead, the memory model is incorporated directly
into the HPS SDRAM interface simulation modules. The memory instance incorporated into the HPS
model is in the simulation model hierarchy at:
inst/mem/
Simulation of the FPGA-to-SDRAM interfaces requires that you first bring the interfaces out of reset,
otherwise transactions cannot occur. Connect the H2F reset to the F2S port resets and add a stage to your
testbench to assert and deassert the H2F reset in the HPS. Appropriate Verilog code is shown below:
initial
begin
// Assert reset
<base name>.hps.fpga_interfaces.h2f_reset_inst.reset_assert();
// Delay
#1
// Deassert reset
<base name>.hps.fpga_interfaces.h2f_reset_inst.reset_deassert();
end
Generating a Preloader Image for HPS with EMIF
To generate a Preloader image for an HPS-based external memory interface, you must complete the
following tasks:
SDRAM Controller Subsystem
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HPS Memory Interface Simulation
hps_0/fpga_interfaces/f2sdram/hps_sdram_
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