Altera cyclone V Technical Reference page 845

13-24
NAND Flash Controller Performance Registers
NAND Flash Controller Performance Registers
These registers specify the size of the bursts on the device interface, which maximizes the overall
performance on the NAND flash controller.
Initialize the
of the device interface by minimizing the number of bursts required to transfer a page.
Interrupt and DMA Enabling
Prior to initiating any data operation on the NAND flash controller, the software must set appropriate
interrupt status register bits. If the software uses the DMA logic in the flash controller, then the
appropriate DMA enable and interrupts bits in the register space must be set.
1. Set the
interrupt.
2. Set the relevant bits of the
if the flash controller is in interrupt mode. Altera recommends that the software reads back this register
to ensure clearing an interrupt status. This recommendation applies also to an interrupt service routine.
3. Enable DMA if your application needs DMA mode. Enable DMA by setting the
dma_enable
ensure that the mode change is accepted before sending a DMA command to the flash controller.
4. If the DMA is enabled, then set up the appropriate bits of the
Order of Interrupt Status Bits Assertion
The following interrupt status bits, in the
order of interrupt bit setting:
1.
time_out
2.
dma_cmd_comp
3.
pipe_cpybck_cmd_comp
command completes.
4.
locked_blk
5.
INT_act
ready_busy
6.
rst_comp
completed.
7. For an erase command:
a.
erase_fail
b.
erase_comp
8. For a program command:
a.
locked_blk
b.
pipe_cmd_err
c.
page_xfer_inc
d.
program_fail
e.
pipe_cpybck_cmd_comp
f.
program_comp
g.
dma_cmd_comp
9. For a read command:
(38) This interrupt status bit is the last to be asserted during a DMA operation to transfer data.
Altera Corporation
flash_burst_length
bit in the
flag global_int_enable
intr_en0
register in the group. Altera recommends that the software reads back this register to
dma
—All other interrupt bits are set to 0 when the watchdog
—This bit signifies the completion of data transfer sequence.
—This bit is asserted when a copyback command or the last page of a pipeline
—This bit is asserted when a program (or erase) is performed on a locked block.
—No relationship with other interrupt status bits. Indicates a transition from 0 to 1 on the
pin value for that flash device.
—No relationship with other interrupt status bits. Occurs after a reset command has
(if failure)
(if performed on a locked block)
(if the pipeline sequence is broken by a MAP01 command)
(at the end of each page data transfer)
(if failure)
(If DMA enabled)
register in the group to a value which maximizes the performance
dma
register in the
register in the
status
register in the
intr_status0
group to 1, to enable global
config
group to 1 before initiating any operations
flag
register in the
dma_intr_en
group, are listed in the
status
bit is asserted.
time_out
(38)
cv_5v4
2016.10.28
bit of the
group.
dma
NAND Flash Controller
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