Cortex-A9 Processor - Altera cyclone V Technical Reference

9-6

Cortex-A9 Processor

Cortex-A9 Processor
Each Cortex-A9 processor includes the following hardware blocks:
• ARM NEON
v3 double-precision floating point unit for media and signal processing acceleration
• Single- and double-precision IEEE-754 floating point math support
• Integer and polynomial math support
• Level 1 (L1) cache with parity checking
• 32 KB four-way set-associative instruction cache
• 32 KB four-way set-associative data cache
• CoreSight
Each Cortex-A9 processor supports the following features:
• Dual-issue superscalar pipeline with advanced branch prediction
• Out-of-order (OoO) dispatch and speculative instruction execution
• 2.5 million instructions per second (MIPS) per MHz, based on the Dhrystone 2.1 benchmark
• 128-entry translation lookaside buffer (TLB)
• TrustZone security extensions
• Configurable data endianness
• Jazelle
®
• The Cortex-A9 processor architecture supports the following instruction sets:
• The ARMv7-A performance-optimized instruction set
• The memory-optimized Thumb
• Improves energy efficiency
• 31% smaller memory footprint
• 38% faster than the original Thumb instruction set
• The Thumb instruction set—supported for legacy applications
• Each processor core in the Altera HPS includes an MMU to support the memory management require‐
ments of common modern operating systems.
The Cortex-A9 processors are designated CPU0 and CPU1.
Related Information
ARM Infocenter
Detailed documentation of ARM Cortex-A9 series processors is available on the ARM Infocenter website.
Reset
When a cold or warm reset is issued in the MPU, CPU0 is released from reset automatically. If CPU1 is
present, then its reset signals are left asserted when a cold or warm reset is issued. After CPU0 comes out
of reset, it can deassert CPU1's reset signals by clearing the
(
mpumodrst
Related Information
Reset Manager
Altera Corporation
single instruction, multiple data (SIMD) coprocessor with vector floating-point (VFP)
™
Program Trace Macrocell (PTM) supporting instruction trace
™
DBX Extensions for byte-code dynamic compiler support
) register in the Reset Manager.
on page 3-1
-2 mixed instruction set
®
CPU1
bit in the MPU Module Reset
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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