Altera cyclone V Technical Reference page 794

11-56
dramintr
dramsts Fields
Bit
4
corrdrop
3
dbeerr
2
sbeerr
1
calfail
0
calsuccess
dramintr
This register can enable, disable and clear the SDRAM error interrupts.
Module Instance
sdr
Offset:
0x503C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
This bit is set to 1 when any auto-corrections have
been dropped.
This bit is set to 1 when any ECC double bit errors are
detected.
This bit is set to 1 when any ECC single bit errors are
detected.
This bit is set to 1 when the PHY is unable to
calibrate.
This bit will be set to 1 if the PHY was able to success‐
fully calibrate.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
0xFFC20000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Access
Register Address
0xFFC2503C
21 20 19 18
5 4 3 2
intrc corrd dbema
lr ropma sk
sk
RW RW
0x0 RW 0x0
0x0
SDRAM Controller Subsystem
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
sbema intren
sk
RW 0x0
RW
0x0
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