Nand Flash Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
If the device command set requires the NAND flash controller to issue a load command for the last page in
the pipeline read command, a
completes.
The pipeline commands sequence advanced commands in the device, such as cache and multi-plane.
When the NAND flash controller receives a multi-page read or write pipeline command, it sequences
commands sent to the device depending on settings in the following registers in the
•
cache_read_enable
•
cache_write_enable
•
multiplane_operation
For a device that supports cache read sequences, the
set to 1. The NAND flash controller sequences each multi-page pipeline read command as a cache read
sequence. For a device that supports cache program command sequences,
set. The flash controller sequences each multi-page write pipeline command as a cache write sequence.
For a device that has multi-planes and supports multi-plane program commands, the NAND flash
controller register
pipeline write command, the flash controller sequences the device with multi-plane program commands
and expects that the host transfers data to the flash controller in an even-odd block increment addressing
mode.

NAND Flash Controller Address Map and Register Definitions

The address map and register definitions for the NAND Flash Controller consist of the following regions:
NAND Controller Module Data (AXI Slave) Address Map
This address space is allocated for indexed addressing by the NAND flash controller.
NAND Flash Controller Module Registers (AXI Slave) Address Map
Registers in the NAND Flash Controller module accessible via its register AXI slave
Related Information
Introduction to the Hard Processor System
•
The base addresses of all modules are also listed in the Introduction to the Hard Processor System
chapter.
• Cyclone V Address Map and Register Definitions
Web-based address map and register definitions
NAND Controller Module Data (AXI Slave) Address Map
This address space is allocated for indexed addressing by the NAND flash controller.
Table 13-18: NAND Controller Module Data Space Address Range
Module Instance
NAND_DATA
NAND Flash Controller
Send Feedback
NAND Flash Controller Address Map and Register Definitions
interrupt is generated after the last page load operation
load_comp
, in the
multiplane_operation
Start Address
0xFF900000
bit of the
flag cache_read_enable
group, must be set. On receiving the multi-page
config
on page 13-33
on page 13-34
on page 1-1
group:
config
register must be
must be
cache_write_enable
End Address
0xFF9FFFFF
Altera Corporation
13-33