Altera cyclone V Technical Reference page 199

cv_5v4
2016.10.28
CAN Controller
The switching between the CAN controller and FPGA interfaces is controlled by the system manager. The
DMA channels can be dedicated to the FPGA or to one of the four CAN interfaces.
Table 5-1: Peripheral Request Interface Mapping
DMA Channel
Channel 0
Channel 1
Channel 2
Channel 3
The register controls the MUX that selects whether FPGA or CAN connects to each of the DMA
ctrl
peripheral request interfaces.
Table 5-2: Control Register (ctrl)
FPGA
CAN
Related Information
DMA Controller
•
Peripheral Request Interface
•
• CAN Controller
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
For more information on the System Manger's registers, refer to the Cyclone V SoC HPS Address Map
and Register Definitions page.
EMAC
You can program the
f2s_ptp_ref_clk
You can use the system manager's
by setting or clearing the (
attributes for the master transactions of the DMA engine in the EMAC controllers.
Note: Register bits must be accessed only when the master interface is guaranteed to be in an inactive
state.
The
phy_intf_sel
when the peripheral is released from reset. The
internally or externally generated. The
core is pulled out of reset.
System Manager
Send Feedback
FPGA 4
FPGA 5
FPGA 6
FPGA 7
Interface
on page 16-1
on page 16-10
on page 25-1
register to select either
emac_global
from the FPGA fabric as the source of the IEEE 1588 reference clock for each EMAC.
l3master
arcache, awcache
bit is programmed to select between a GMII (MII), RGMII or RMII PHY interface
ptp_ref_sel
Peripheral
CAN0 interface 1
CAN0 interface 2
CAN1 interface 1
CAN1 interface 2
0x0
0x1
emac_ptp_clk
register to control the EMAC's
) and (
arprot, awprot
bit selects if the timestamp reference is
ptp_ref_sel
bit must be set to the correct value before the EMAC
CAN Controller
CAN Controller
Value
from the Clock Manager or
and
ARCACHE AWCACHE
) bits. These bits define the cache
Altera Corporation
5-5
signals,