Altera cyclone V Technical Reference page 789

cv_5v4
2016.10.28
Offset:
0x5010
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
pwrdownexit
RW 0x0
dramtiming4 Fields
Bit
23:20
minpwrsavecycles
19:10
pwrdownexit
9:0
selfrfshexit
lowpwrtiming
This register controls the behavior of the low power logic in the controller.
Module Instance
sdr
Offset:
0x5014
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
SDRAM Controller Subsystem
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
Name
The minimum number of cycles to stay in a low
power state. This applies to both power down and
self-refresh and should be set to the greater of tPD
and tCKESR.
The power down exit cycles, tXPDLL.
The self refresh exit cycles, tXS.
0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
minpwrsavecycles
RW 0x0
9 8 7 6
Description
Base Address
lowpwrtiming
21 20 19 18
pwrdownexit
RW 0x0
5 4 3 2
selfrfshexit
RW 0x0
Access
Register Address
0xFFC25014
11-51
17 16
1 0
Reset
RW 0x0
RW 0x0
RW 0x0
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