Altera cyclone V Technical Reference page 788

11-50
dramtiming3
dramtiming3
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
Module Instance
sdr
Offset:
0x500C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
tmrd
RW 0x0
dramtiming3 Fields
Bit
22:19
tccd
18:15
tmrd
14:9
trc
8:4
tras
3:0
trtp
dramtiming4
This register implements JEDEC standardized timing parameters. It should be programmed in clock
cycles, for the value specified by the memory vendor.
Module Instance
sdr
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
trc
RW 0x0
Name
The CAS to CAS delay time.
Mode register timing parameter.
The activate to activate timing parameter.
The activate to precharge timing parameter.
The read to precharge timing parameter.
Base Address
0xFFC20000
Bit Fields
25 24 23 22
9 8 7 6
tras
RW 0x0
Description
Base Address
0xFFC20000
Register Address
0xFFC2500C
21 20 19 18
tccd
RW 0x0
5 4 3 2
Access
Register Address
0xFFC25010
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
tmrd
RW 0x0
1 0
trtp
RW 0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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