Altera Cyclone V User Manual
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Altera Cyclone V User Manual

Hard ip for pci express
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Cyclone V Hard IP for PCI Express User Guide
Cyclone V Hard IP for PCI Express
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document last updated for Altera Complete Design Suite version:
11.1
Document publication date:
November 2011
UG-01110-1.0
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Summary of Contents for Altera Cyclone V

  • Page 1 Cyclone V Hard IP for PCI Express User Guide Cyclone V Hard IP for PCI Express User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document last updated for Altera Complete Design Suite version: 11.1 Document publication date: November 2011 UG-01110-1.0...
  • Page 2 © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Customizing the Endpoint in Qsys ............2–9 Specifying the Parameters for the Cyclone V Hard IP for PCI Express ..... 2–10 Specifying the Parameters for the Example Design .
  • Page 4 Receive Buffer Reordering ..............8–4 Cyclone V Hard IP for PCI Express...
  • Page 5 How to Contact Altera ........
  • Page 6 ContentsContents Cyclone V Hard IP for PCI Express November 2011 Altera Corporation User Guide...

  • Page 7: Chapter 1. Datasheet

    The performance is scalable based on the number of lanes that is implemented. Altera offers a configurable hard IP block in Cyclone V devices for both Endpoints and Root Ports that complies with the PCI Express Base Specification 2.1.
  • Page 8 TLP headers. The purpose of the Cyclone V Hard IP for PCI Express User Guide is to explain how to use the Cyclone V Hard IP for PCI Express and not to explain the PCI Express protocol.

  • Page 9: Release Information

    Stratix V Hard IP for PCI Express User Guide ■ Cyclone V Hard IP for PCI Express User Guide ■ Configurations The Cyclone V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers: ■ Physical (PHY) ■...

  • Page 10: Debug Features

    Root Port and the other as a multi-function Endpoint. The FPGA serves as a custom I/O hub for the host CPU. In the Cyclone V FPGA, each peripheral is treated as a function with its own set of Configuration Space registers. Eight multiplexed functions operate using a single PCI Express link.

  • Page 11: Ip Core Verification

    1–4: (1) This is a power-saving mode of operation. (2) Final results pending characterization by Altera for speed grades -2, -3, and -4. Refer to the .fit.rpt file generated by the Quartus II software. For details on installation, refer to the Altera Software Installation and Licensing Manual.
  • Page 12 1–6 Chapter 1: Datasheet Recommended Speed Grades Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 13: Chapter 2. Getting Started

    After you install the Quartus II software for 11.1, you can copy these example designs from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/ cv directory. This walkthrough uses the Gen1 ×4 Endpoint. The Cyclone V Hard IP for PCI Express offers exactly the same feature set in both the MegaWizard and Qsys design flows.
  • Page 14 2–2 Chapter 2: Getting Started Figure 2–1 illustrates the steps necessary to customize the Cyclone V Hard IP for PCI Express and run the example design. Figure 2–1. MegaWizard Plug-In Manager and Qsys Design Flows Select Design Flow MegaWizard Qsys Flow...

  • Page 15: Megawizard Plug-In Manager Design Flow

    MegaWizard Plug-In Manager Design Flow MegaWizard Plug-In Manager Design Flow This section guides you through the steps necessary to customize the Cyclone V Hard IP for PCI Express and run the example testbench, starting with the creation of a Quartus II project. It includes the following steps: ■...

  • Page 16: Customizing The Endpoint In The Megawizard Plug-In Manager Design Flow

    6. Specify a variation name for output files <working_dir>/example_design/ <variation name>. For this walkthrough, specify <working_dir>/example_design/ gen1_x4. 7. Click Next to open the parameter editor for the Cyclone V Hard IP for PCI Express. 8. Specify the System Settings values listed inTable 2–1.
  • Page 17 BAR2 Type 32-bit non-prefetchable memory BAR2 Size 1 KByte - 10 bits 15. You can leave Func0 BAR3 through Func0 BAR5 and the Func0 Expansion ROM Disabled. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 18: Understanding The Files Generated

    Generally, a single .qip file is generated for each IP core. Understanding the Files Generated Figure 2–2 illustrates the directory structure created for this design after you generate the Cyclone V Hard IP for PCI Express. Generation creates three directories: <working_dir>/<variant_name> includes the files for synthesis. ■ ■...
  • Page 19 MegaWizard Plug-In Manager Design Flow Figure 2–2 illustrates this directory structure. Figure 2–2. Directory Structure for Cyclone V Hard IP for PCI Express IP Simulation Model and Design Example <working_dir> <variant_name>.v or .vhd = gen1_x4.v, the parameterized endpoint <variant_name>.qip = lists all files used in the Gen1 x4 endpoint <variant_name>.bsf = gen1_x4.bsf, a block symbol file for the parameterized endpoint...
  • Page 20 5. To close the APPS component, click the X in the upper right-hand corner of the parameter editor. Go to “Generating the Simulation Model Using Qsys” on page 2–16 for instructions on system simulation. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 21: Qsys Design Flow

    PCI Ex r Qsys filters the component library and shows all components matching the text string you entered. 6. Click on Cyclone V Hard IP for PCI Express and then click the +Add button. The parameter editor appears. November 2011 Altera Corporation...

  • Page 22: Specifying The Parameters For The Cyclone V Hard Ip For Pci Express

    2–16. The completed Qsys systems are located in the following directory: <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design/cv. Specifying the Parameters for the Cyclone V Hard IP for PCI Express This section guides you through the process of specifying parameters for the Cyclone V Hard IP for PCI Express to create a Gen1 ×4 Endpoint.
  • Page 23 10. Specify the Device ID Registers for Func0 listed in Table 2–15. Table 2–15. Device Identification Registers for Func0 (Part 1 of 2) Register Name Value Vendor ID 0x00000000 Device ID 0x00000001 Revision ID 0x00000001 November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 24: Specifying The Parameters For The Example Design

    14. On the Func0 MSI-X tab, turn Implement MSI-X turned off. 15. Click the Finish button. 16. To rename the Cyclone V hard IP for PCI Express, in the Name column of the System Contents tab, right-click on the component name, select Rename, and...

  • Page 25: Completing The Qsys System

    Chapter 2: Getting Started 2–13 Qsys Design Flow 4. To rename the Example design for Avalon-Streaming Cyclone V hard IP for PCI Express component, right-click on the component name, select Rename, and type APPSr Completing the Qsys System The APPS component interfaces connect to the Endpoint variant interfaces with matching names.
  • Page 26 Avalon types. You can connect conduit interfaces to each other inside a Qsys system or export them to make connections to other modules in the design or to FPGA pins. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 27 5. To remove the default clock, on the System Contents tab, click clk_0 and then click button. 6. To save your Qsys system, on the File menu select Save. Type pcie_qsys in the Save dialog box. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 28: Generating The Simulation Model Using Qsys

    Verilog or None Synthesis Create HDL design files for synthesis Turn on this option Create block symbol file (.bsf) Turn on this option Output Directory Path pcie_qsys/pcie_de_gen1_x4_ast64 Simulation pcie_qsys/pcie_de_gen1_x4_ast64/simulation Testbench pcie_qsys/pcie_de_gen1_x4_ast64/testbench Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 29: Quartus Ii Compilation

    Quartus II project and add your Qsys files to that project. Complete the following steps to create your Quartus II project: 1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. 2. Change to the directory that includes your Qsys project, <working_dir>\pcie_qsys.
  • Page 30 In the Family list, select Cyclone V. b. In the Devices list, select Cyclone V GX PCIe. c. In the Available devices list, select5CGXFC7D6F31C7. 10. Click Next to close this page and display the EDA Tool Settings page.

  • Page 31: Modifying The Example Design

    Reconfiguration Lane 3 Root to and from Reconfig Controller Lane 2 Port Embedded to and from Controller Transceiver Lane 1 TX PLL (Avalon-MM slave interface) Lane 0 November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 32 2–20 Chapter 2: Getting Started Modifying the Example Design Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 33: Chapter 3. Parameter Settings

    This chapter describes the parameters which you can set using the MegaWizard Plug-In Manager or Qsys design flow to instantiate a Cyclone V Hard IP for PCI Express IP core. The appearance of the GUI is identical for the two design flows.
  • Page 34 This option is recommended for control and status endpoint applications that don't generate any PCIe requests of their own and only are the target of write and read requests from the root complex. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 35: Port Functions

    Some of these parameters are stored in the Common Configuration Space Header. Text in green are links to these parameters stored in the Common Configuration Space Header. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 36: Device

    Bits are set to show timeout value ranges supported. 0x0000b completion timeout programming is not supported and the function must implement a timeout value in the range 50 s to 50 ms. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 37: Error Reporting

    Table 3–3: (1) Throughout The Cyclone V Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification Revision 2.1 or 3.0. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

  • Page 38: Link

    The default value prior to hardware and firmware initialization is b’00. Writes to this register also cause the port to send the Set_Slot_Power_Limit Message. Refer to Section 6.9 of the for more PCI Express Base Specification Revision 2.1 information. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 39: Power Management

    It sets the read-only value of the Endpoint L0s acceptable latency field of the Device Capabilities register (0x084). The Cyclone V Hard IP for PCI Express does not support the L0s or L1 states. However, in a switched system there may be links connected to Endpoint L0s <...
  • Page 40 16-bit I/O addressing registers. 32-bit I/O addressing Disable Specifies the address widths for the Prefetchable Memory Prefetchable memory 32-bit I/O addressing Base register and Prefetchable Memory Limit register. 64-bit I/O addressing Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 41 Link Capabilities register parameters. Table 3–10. Function Level Reset Parameter Value Description Function level reset On/Off Turn On this option to provide separate reset for this function. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 42 Indicates which of a function’s Base Address registers, located beginning at 0x10 PBA BAR Indicator <5–1>:0 in Configuration Space, is used to map the function’s MSI-X PBA into memory (BIR) space. This field is read-only. Legal range is 0–5. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 43: Chapter 4. Ip Core Architecture

    4. IP Core Architecture November 2011 1101 This chapter describes the architecture of the Cyclone V Hard IP for PCI Express. The Cyclone V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification 2.1.

  • Page 44: Key Interfaces

    4–2 Chapter 4: IP Core Architecture Key Interfaces This chapter provides an overview of the architecture of the Cyclone V Hard IP for PCI Express. It includes the following sections: Key Interfaces ■ Protocol Layers ■ ■ Multi-Function Support Key Interfaces...

  • Page 45: Clocks And Reset

    The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this specification, the Cyclone V Hard IP for PCI Express includes an embedded hard reset controller. For more information about clocks and reset, refer to “Clock Signals”...

  • Page 46: Protocol Layers

    1. The Transaction Layer receives a TLP from the Data Link Layer. 2. The Transaction Layer determines whether the TLP is well formed and directs the packet based on traffic class (TC). Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 47: Configuration Space

    Specification Revision 2.1. Refer To “Configuration Space Register Content” on page 6–1 or Chapter 7 in the Express Base Specification 2.1 for the complete content of these registers. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 48: Data Link Layer

    Management State Machine Function Tx Flow Control Credits DLLP Rx Flow Control Credits RX Datapath Checker Transaction Layer Packet Checker Rx Packets Rx Transation Layer Packet Description & Data Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 49: Physical Layer

    ACK/NAK FC DLLP (low priority) Physical Layer The Physical Layer is the lowest level of the Cyclone V Hard IP for PCI Express. It is the layer closest to the link. It encodes and transmits packets across a link and accepts and decodes received packets.
  • Page 50 The Physical Layer integrates both digital and analog elements. Intel designed the PIPE interface to separate the MAC from the PHY. The Cyclone V Hard IP for PCI Express complies with the PIPE interface specification. Cyclone V Hard IP for PCI Express...
  • Page 51 RX alignment function recreates a 64-bit data word which is sent to the DLL. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 52: Multi-Function Support

    4–10 Chapter 4: IP Core Architecture Multi-Function Support Multi-Function Support The Cyclone V Hard IP for PCI Express supports up to eight functions for Endpoints. You set up the each function under the Port Functions heading in the parameter editor. You can configure Cyclone V devices to include both Native and Legacy Endpoints.
  • Page 53 5. IP Core Interfaces November 2011 1101 This chapter describes the signals that are part of the Cyclone V Hard IP for PCI Express IP core. Figure 5–1 on page 5–2 illustrates the top-level signals IP core. Because the Cyclone V Hard IP for PCI Express offers exactly the same feature set in...

  • Page 54: Chapter 5. Ip Core Interfaces

    Cyclone V Hard IP for PCI Express IP core. Signal names that include <a> also exist for functions 1 to 7. Figure 5–1. Signals in the Cyclone V Hard IP for PCI Express with Avalon-ST Interface Cyclone V Hard IP for PCI Express, Avalon-ST Interface...

  • Page 55: Avalon-St Rx Interface

    When an uncorrectable ECC error is detected, rx_st_err is rx_st_err error asserted for at least 1 cycle while rx_st_valid is asserted. Altera recommends resetting the Cyclone V Hard IP for PCI Express IP core when an uncorrectable (double-bit) ECC error is detected. Component Specific Signals The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests.
  • Page 56 This signal is deprecated. component Specifies which function the rx_st_bar signal applies to. rx_bar_dec_func_num specific For more information about the Avalon-ST protocol, refer to the Avalon Interface Specifications. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 57: Data Alignment And Timing For The 64-Bit Avalon-St Rx Interface

    5–5 Avalon-ST RX Interface To facilitate the interface to 64-bit memories, the Cyclone V Hard IP for PCI Express aligns data to the qword or 64 bits by default; consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment.
  • Page 58 64-bit bus. Figure 5–5. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLP with Qword Aligned Address coreclkout header1 header3 data1 rx_st_data[63:32] header0 header2 data0 rx_st_data[31:0] rx_st_sop rx_st_eop rx_st_be[7:4] rx_st_be[3:0] Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 59 Figure 5–7 illustrates the timing of the RX interface when the Application Layer backpressures the Cyclone V Hard IP for PCI Express by deasserting rx_st_ready. The rx_st_valid signal must deassert within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.

  • Page 60: Avalon-St Tx Interface

    Indicates first cycle of a TLP when asserted in the same start of tx_st_sop cycle with tx_st_valid. packet Indicates last cycle of a TLP when asserted in the same end of tx_st_eop cycle with tx_st_valid. packet Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 61 Figure 5–12 on page 5–13 for the timing of this signal. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals. If no other delays are added to the ready-valid latency, the resulting delay corresponds to a readyLatency of 2.
  • Page 62 MRd requests must be less than this value to prevent RX FIFO overflow. Note to Table 5–4: (1) To be Avalon-ST compliant, your application have a readyLatency of 1 or 2 cycles. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 63: Avalon-St Packets To Pci Express Tlps

    (3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11} (4) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} (5) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} (6) Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8} November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 64 Figure 5–11. 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-Dword Header with Non-Qword Aligned Address coreclkout Header 1 Header3 Data0 Data2 tx_st_data[63:32] Header 0 Header2 Data1 tx_st_data[31:0] tx_st_sop tx_st_eop Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 65: Root Port Mode Configuration Requests

    Avalon-ST TX Interface Figure 5–12 illustrates the timing of the TX interface when the Cyclone V Hard IP for PCI Express IP core backpressures the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is asserted.

  • Page 66: Ecrc Forwarding

    Table 5–5. Clock Signals Hard IP Implementation Signal Description Reference clock for the Cyclone V Hard IP for PCI Express. It must have the frequency refclk specified under the System Settings heading in the parameter editor. Clocks the Application Layer. You must drive this clock with coreclkout.
  • Page 67 PCI Express in Cyclone V devices. It resets the datapath and control registers. This signal is required for CvP. Cyclone V devices have 1 or 2 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal.
  • Page 68 10001: loopback.entry ■ 10010: loopback.active ■ 10011: loopback.exit ■ 10100: hot.reset ■ 10101: L0s ■ 10110: L1.entry ■ 10111: L1.idle ■ 11000: L2.idle ■ 11001: L2.transmit.wake ■ 11010: recovery.speed ■ Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 69: Ecc Error Signals

    Application Layer MSI traffic class. This signal indicates the traffic class used to send the tl_app_msi_tc[2:0] MSI (unlike INTX interrupts, any traffic class can be used to send MSIs). November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 70: Interrupts For Root Ports

    Device Control register. If enabled, serr_out is asserted for a single clock serr_out cycle when a system error occurs. System errors are described in the PCI Express Base Specification 1.1 or 2.0. in the Root Control register. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 71: Completion Side Band Signals

    Table 5–10 describes the signals that comprise the completion side band signals for the Avalon-ST interface. The Cyclone V Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors.

  • Page 72: Transaction Layer Configuration Space Signals

    The toggle edge marks where the tl_cfg_ctl data changes. You tl_cfg_ctl_wr can use this edge as a reference to determine when the data is safe to sample. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 73 If this slot has no power controller, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the Slot Capability register should be disabled. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 74 [46:31] Slot clock configuration cfg_linkcsr_func0[31:16] ■ Link Training ■ Undefined ■ Negotiated Link Width (6 bits) ■ Link Speed (4 bits) ■ [30] Records the current de-emphasis level. cfg_link2csr_func0[16] Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 75: Configuration Space Register Access Timing

    Configuration Space register information is being driven onto tl_cfg_ctl. Figure 5–15. tl_cfg_ctl Timing coreclkout tl_cfg_add[3:0] . . 00... 00... 00... 7F... 00... 00... 00000000 00000000 tl_cfg_ctl[31:0] November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 76: Configuration Space Register Access

    Device Control for the PCI Express cfg_devcsr_func<n> page 6–4 capability structure. cft_dev2csr[31:16] is status 2 and cfg_dev2csr[15:0] Table 6–8 on cfg_dev2csr is device control 2 for the PCI Express capability structure. page 6–4 Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 77 The upper 12 bits of the memory limit register of the Type1 Table 3–7 on Configuration Space. This register is only available in Root Port page 3–8 cfg_np_lim mode. EXP ROM November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 78 Table A–5 on Bus/Device Number captured by or programmed in the Hard IP. page A–2 cfg_busdev 0x08 Table 5–15 shows the layout of the Configuration MSI Control Status register. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 79: Lmi Signals

    LMI interface is used to write log error descriptor information in the TLP header log registers. The LMI access to other registers is intended for debugging, not normal operation. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 80 LMI interface. Table 5–16. LMI Interface (Part 1 of 2) Signal Width Description Data outputs lmi_dout Read enable input lmi_rden Write enable input lmi_wren Write execution done/read data valid lmi_ack Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 81: Lmi Read Operation

    Read-only bits are not affected. LMI write operations are not recommended for use during normal operation with the exception of AER header logging. Figure 5–18. LMI Write coreclkout lmi_wren lmi_din[31:0] lmi_addr[14:0] lmi_ack November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 82: Power Management Signals

    Power Management Auxiliary Power: This signal can be tied to 0 because the L2 power pm_auxpwr state is not supported. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 83 Then, the Application Layer sends the PME_to_ack message to the Root Port by asserting pme_to_cr. Figure 5–19. pme_to_sr and pme_to_cr in an Endpoint IP core pme_to_sr hard pme_to_cr November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 84: Physical Layer Interface Signals

    MegaWizard Plug-In Manager generates a SERDES variation file, <variation>_serdes.<v or vhd >, in addition of the Hard IP variation file, <variation>.<v or vhd>. For Cyclone V GX devices the SERDES entity is included in the library files for PCI Express.

  • Page 85: Pipe Interface Signals

    Transmit detect receive <n>. This signal tells the PHY layer to start a txdetectrx0 receive detection operation or to begin loopback. Transmit electrical idle <n>. This signal forces the TX output to electrical txelecidle idle. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 86 Power down <n>. This signal requests the PHY to change its power state powerdown0[1:0] to the specified state (P0, P0s, P1, or P2). Transmit de-emphasis selection. The Cyclone V Hard IP for PCI Express sets the value for this signal based on the indication received from the tx_deemph0 other end of the link during the Training Sequences (TS).
  • Page 87 (1) Signals that include lane number 0 also exist for lanes 1-7. (2) These signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 88: Test Signals

    Table 5–23 describes the test signals. Altera recommends that you use the test_in signals for debug or non-critical status monitoring purposes such as LED displays of PCIe link status. They should not be used for design function purposes. Use of these signals will make it more difficult to close timing on the design.

  • Page 89: Chapter 6. Register Descriptions

    Subsystem ID and Subsystem Vendor ID 0x0C8-0x7FC Reserved 0x800:0x834 Advanced error reporting (AER) (optional) 0x838:0xFFF Reserved For comprehensive information about these registers, refer to Chapter 7 of the Express Base Specification Revision 2.1. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express...
  • Page 90 Func0–Func7 BARs and Expansion ROM 0x014 Func0–Func7 BARs and Expansion ROM Secondary Latency Subordinate Bus Secondary Bus 0x018 Primary Bus Number Timer Number Number 0x01C Secondary Status I/O Limit I/O Base Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 91 Note to Table 6–4: (1) Specifies the byte offset within Cyclone V Hard IP for PCI Express IP core’s address space. (2) Refer to Table 6–9 on page 6–5 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express Base Specification 2.0.
  • Page 92 Device Control 2 0x08C Link 0x090 Link Status Link Control 0x094 Slot 0x098 Slot Status Slot Control 0x09C Root Capabilities Root Control 0x0A0 Root Status 0x0A4 Device Capabilities 2 Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 93: Correspondence Between Configuration Space Registers And The Pcie Spec 2.1

    0x300:0x33C Port VC4 arbitration table (Reserved) Port Arbitration Table 0x340:0x37C Port VC5 arbitration table (Reserved) Port Arbitration Table 0x380:0x3BC Port VC6 arbitration table (Reserved) Port Arbitration Table November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 94 Type 1 Configuration Space Header 0x030 I/O Limit Upper 16 Bits I/O Base Upper 16 Bits Type 1 Configuration Space Header 0x034 Reserved Capabilities PTR Type 1 Configuration Space Header Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 95 Root Error Command Root Error Command Register 0x830 Root Error Status Root Error Status Register Error Source Identification Register Correctable 0x834 Error Source Identification Register Error Source ID Register November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 96 6–8 Chapter 6: Register Descriptions Correspondence between Configuration Space Registers and the PCIe Spec 2.1 Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 97: Reset

    5–14. Reset The Cyclone V Hard IP for PCI Express IP core includes an embedded reset controller to handle the initial reset of the PMA, PCS, and Hard IP for PCI Express IP core. The pin_perst signal which is driven from one of the two designated nPERST pins of the device initiates reset.

  • Page 98: Clocks

    Configuration ■ Space registers. The Cyclone V embedded reset sequence meets the 100 ms configuration time specified in the PCI Express Base Specification 2.1. Clocks In accordance with the PCI Express Base Specification 2.1, you must provide a 100 MHz...

  • Page 99: P_Clk

    Layer, and the Application Layer. Ideally, the pld_clk drives all user logic in the Application Layer, including other instances of the Cyclone V Hard IP for PCI Express and memory interfaces. The pld_clk input clock pin is typically generated from the coreclkout_hip output clock pin.
  • Page 100 7–4 Chapter 7: Reset and Clocks Clocks Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 101: Supported Message Types

    8. Transaction Layer Protocol (TLP) Details November 2011 1101 This chapter provides detailed information about the Cyclone V Hard IP for PCI Express. TLP handling. It includes the following sections: Supported Message Types ■ ■ Transaction Layer Routing Rules ■...
  • Page 102 Set Slot Power Receive In Root Port mode, through software. Limit Vendor-defined Messages Transmit Transmit Vendor Defined Type 0 Receive Receive Transmit Transmit Vendor Defined Type 1 Receive Receive Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 103: Transaction Layer Routing Rules

    Layer logic processes the requests and generates the read completions, if needed. ■ In Endpoint mode, received Type 0 Configuration requests from the PCI Express upstream port route to the internal Configuration Space and the Cyclone V Hard IP for PCI Express generates and transmits the completion. ■...

  • Page 104: Receive Buffer Reordering

    Hard IP Spec Hard IP Spec Hard IP Spec Hard IP (10) Memory Write or (11) (11) (11) (11) (11) (11) Message (12) (12) (12) (12) (12) (12) Request Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 105 MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and are indistinguishable from them in terms of flow control, ordering, and data integrity. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 106 8–6 Chapter 8: Transaction Layer Protocol (TLP) Details Receive Buffer Reordering Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 107: Chapter 9. Optional Features

    Error TLP Forward to Application Layer Forwarding Status Enable none Forwarded good Forwarded without its ECRC Forwarded without its ECRC none Forwarded good Forwarded without its ECRC Not forwarded November 2011 Altera Corporation Cyclone V Hard IP for PCI Express...

  • Page 108: Ecrc On The Tx Path

    Connected components that include IP blocks for PCI Express need not support the same number of lanes. The ×4 variations support initialization and operation with components that have 1, 2, or 4 lanes. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...
  • Page 109 9–3 Lane Initialization and Reversal The Cyclone V Hard IP for PCI Express supports lane reversal, which permits the logical reversal of lane numbers for the ×1, ×2, and ×4. Lane reversal allows more flexibility in board layout, reducing the number of signals that must cross over each other when routing the PCB.
  • Page 110 9–4 Chapter 9: Optional Features Lane Initialization and Reversal Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 111: Chapter 10. Interrupts

    Interrupts for Endpoints The Cyclone V Hard IP for PCI Express provides support for PCI Express legacy interrupts, MSI, and MSI-X interrupts when configured in Endpoint mode. The MSI, MSI-X, and legacy interrupts are mutually exclusive. After power up, the Hard IP block...
  • Page 112 In this case, you must design the Application Layer to use only two allocated messages. Figure 10–3. MSI Request Example Root Complex Root Endpoint Port 8 Requested Interrupt 2 Allocated Block Interrupt Register Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 113: Msi-X

    Legacy Interrupts Legacy interrupts are signaled on the PCI Express link using message TLPs that are generated internally by the Cyclone V Hard IP for PCI Express IP core. The app_int_sts input port controls interrupt generation. When the input port asserts app_int_sts, it causes an Assert_INTA message TLP to be generated and sent upstream.

  • Page 114: Interrupts For Root Ports

    Traffic Class. For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data. Interrupts for Root Ports In Root Port mode, the Cyclone V Hard IP for PCI Express IP core receives interrupts through two different mechanisms: ■...
  • Page 115 The Root Error Status register reports the status of error messages. The Root Error Status register is part of the PCI Express AER Extended Capability structure. It is located at offset 0x830 of the Configuration Space registers. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 116 10–6 Chapter 10: Interrupts Interrupts for Root Ports Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 117: Chapter 11. Flow Control

    Consumed Registers exist for each of the six types of Flow Control: ■ Posted Headers ■ Posted Data Non-Posted Headers ■ ■ Non-Posted Data ■ Completion Headers ■ Completion Data November 2011 Altera Corporation Cyclone V Hard IP for PCI Express...
  • Page 118 There are separate Credit Allocated Registers for the header and data credits. 5. The value in the Credit Allocated Registers is used to create an FC Update DLLP. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 119: Throughput Of Non-Posted Reads

    (or at least offering enough non-posted header credits) to cover this delay. However, much of the delay encountered in this loop is well outside the Cyclone V Hard IP for PCI Express and is very difficult to estimate. PCI Express switches can be inserted in this loop, which makes determining a bound on the delay more difficult.
  • Page 120 Application Layer and by the maximum read request size that can be issued. The number of header tag values that can be in use is also limited by the Cyclone V Hard IP for PCI Express. You can specify 32 or 64 tags though configuration software to restrict the Application Layer to use only 32 tags.

  • Page 121: Chapter 12. Error Handling

    Each PCI Express compliant device must implement a basic level of error management and can optionally implement advanced error management. The Altera Cyclone V Hard IP for PCI Express implements both basic and advanced error reporting. Given its position and role within the fabric, error handling for a Root Port is more complex than that of an Endpoint.

  • Page 122: Physical Layer Errors

    This error occurs when a sequence number specified by the Ack/Nak Uncorrectable Data Link Layer protocol block in the Data Link Layer (AckNak_Seq_Num) does not correspond to (fatal) an unacknowledged TLP. (Refer to “Data Link Layer” on page 4–6.) Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 123: Transaction Layer Errors

    A 64-bit memory transaction which the 32 MSBs of an address are ■ set to 0. A memory transaction that does not match a Windows address ■ November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 124 A TLP in which the type and length fields do not correspond with ■ the total length of the TLP. A TLP in which the combination of format and type is not specified by ■ the PCI Express specification. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 125: Error Reporting And Data Poisoning

    The poisoned bit is set on a received completion TLP. ■ Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit TLPs are similarly sent to the link. November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...

  • Page 126: Uncorrectable And Correctable Error Status Bits

    Rsvd Header Log Overflow Status Corrected Internal Error Status Advisory Non-Fatal Error Status Replay Timer Timeout Status REPLAY_NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 127: Chapter 13. Debugging

    Typically, PCI Express hardware bring-up involves the following steps: 1. System reset 2. Linking training 3. BIOS enumeration The following sections, describe how to debug the hardware bring-up flow. Altera recommends a systematic approach to diagnosing bring-up issues as illustrated in Figure 13–1.
  • Page 128 ■ / txdatak<n>[1:0] —These signals show the data and control txdata<n>[15:0] being transmitted from the Cyclone V Hard IP for PCI Express to the other device. / rxdatak<n>[1:0] —These signals show the data and control ■ rxdata<n>[15:0] received by Hard P block from the other device.

  • Page 129: Use Third-Party Pcie Analyzer

    Both FPGA programming (configuration) and the initialization of a PCIe link require time. There is some possibility that Altera FPGA including a Hard IP block for PCI Express may not be ready when the OS/BIOS begins enumeration of the device tree.
  • Page 130 13–4 Chapter 13: Debugging Hardware Bring-Up Issues Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 131: Tlp Packet Format Without Data Payload

    0 0 0 0 T Byte 0 0 0 1 0 0 0 0 1 0 Length Byte 4 Requester ID Last BE First BE Byte 8 Address[63:32] Byte 12 Address[31:2] November 2011 Altera Corporation Cyclone V Hard IP for PCI Express...
  • Page 132 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Byte 0 0 0 0 0 1 0 1 1 0 0 0 0 0 TD Length Byte 4 Completer ID Status Byte Count Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 133: Tlp Packet Format With Data Payload

    0 0 0 0 0 0 0 0 0 0 0 0 0 1 Byte 4 0 0 0 0 First BE Requester ID Byte 8 Address[31:2] Byte 12 Reserved November 2011 Altera Corporation Cyclone V Hard IP for PCI Express User Guide...
  • Page 134 Length Byte 4 Requester ID Message Code Byte 8 Vendor defined or all zeros for Slot Power Limit Byte 12 Vendor defined or all zeros for Slots Power Limit Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

  • Page 135: Additional Information

    (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
  • Page 136 A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. Cyclone V Hard IP for PCI Express November 2011 Altera Corporation...

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