Interrupts - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Hardware Reset
Each of the USB OTG controllers has one reset input from the reset manager. The reset signal is asserted
during a cold or warm reset event. The reset manager holds the controllers in reset until software releases
the resets. Software releases resets by clearing the appropriate USB bits in the Peripheral Module Reset
Register (
permodrst
The reset input resets the following blocks:
• The master and slave interface logic
• The integrated DMA controller
• The internal FIFO buffers
• The CSR
The reset input is synchronized to the
ULPI clock within the USB OTG controller and is used to reset the ULPI PHY domain logic.
Software Reset
Software can reset the controller by setting the Core Soft Reset (
( ) in the Global Registers (
grstctl
Software resets are useful in the following situations:
• A PHY selection bit is changed by software. Resetting the USB OTG controller is part of clean-up to
ensure that the PHY can operate with the new configuration or clock.
• During software development and debugging.
Taking the USB 2.0 OTG Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Related Information
Modules Requiring Software Deassert

Interrupts

Table 18-3: USB OTG Interrupt Conditions
Each USB OTG controller has a single interrupt output. Interrupts are asserted on the conditions shown in
the following table.
Device-initiated remote wakeup is detected.
Session request is detected from the device.
Device disconnect is detected.
USB 2.0 OTG Controller
Send Feedback
) in the HPS reset manager.
usb_mp_clk
) group of the USB OTG controller.
globgrp
on page 3-9
Condition
domain. The reset input is also synchronized to the
) bit in the Reset Register
csftrst
Host mode
Host mode
Host mode
18-11
Hardware Reset
Mode
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