Page 1 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration CV-5V2 101 Innovation Drive Subscribe 2014.01.10 San Jose, CA 95134 Send Feedback www.altera.com...
Page 2: Table Of Contents
TOC-2 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Contents Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...1-1 LAB ................................1-1 MLAB ..............................1-2 Local and Direct Link Interconnects ....................1-3 LAB Control Signals........................1-4 ALM Resources ..........................1-5 ALM Output ............................1-6 ALM Operating Modes ..........................1-7...
Page 3 TOC-3 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Byte Enable in Embedded Memory Blocks....................2-13 Byte Enable Controls in Memory Blocks..................2-13 Data Byte Output...........................2-14 RAM Blocks Operations.......................2-15 Memory Blocks Packed Mode Support....................2-15 Memory Blocks Address Clock Enable Support..................2-15 Document Revision History........................2-17...
Page 4 TOC-4 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Types of Clock Networks........................4-3 Clock Sources Per Quadrant......................4-7 Types of Clock Regions........................4-8 Clock Network Sources........................4-9 Clock Output Connections......................4-11 Clock Control Block........................4-11 Clock Power Down........................4-14 Clock Enable Signals........................4-14 Cyclone V PLLs............................4-16 PLL Physical Counters in Cyclone V Devices................4-16...
Page 5 TOC-5 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Guideline: Ensure Compatible V and V Voltage in the Same Bank......5-18 CCIO CCPD Guideline: Pin Restrictions....................5-18 VREF Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......5-18 Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules............................5-19...
Page 6 TOC-6 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration True LVDS Buffers in Cyclone V Devices..................5-55 Emulated LVDS Buffers in Cyclone V Devices.................5-63 Differential Transmitter in Cyclone V Devices..................5-63 Transmitter Blocks.........................5-63 Serializer Bypass for DDR and SDR Operations...............5-64 Differential Receiver in Cyclone V Devices...................5-65...
Page 7 TOC-7 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration I/O and DQS Configuration Blocks....................6-29 Hard Memory Controller.........................6-30 Features of the Hard Memory Controller..................6-30 Multi-Port Front End........................6-32 Bonding Support..........................6-33 Hard Memory Controller Width for Cyclone V E..............6-35 Hard Memory Controller Width for Cyclone V GX..............6-36 Hard Memory Controller Width for Cyclone V GT..............6-37...
Page 8 TOC-8 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Passive Serial Configuration........................7-20 Passive Serial Single-Device Configuration Using an External Host........7-21 Passive Serial Single-Device Configuration Using an Altera Download Cable....7-21 Passive Serial Multi-Device Configuration................7-22 JTAG Configuration..........................7-24 JTAG Single-Device Configuration.....................7-25 JTAG Multi-Device Configuration.....................7-27...
Page 9 TOC-9 Cyclone V Device Handbook Volume 1: Device Interfaces and Integration CRC_ERROR Pin..........................8-5 Error Detection Registers........................8-5 Error Detection Process........................8-7 Testing the Error Detection Block....................8-8 Document Revision History........................8-9 JTAG Boundary-Scan Testing in Cyclone V Devices.........9-1 BST Operation Control ..........................9-1 IDCODE ............................9-1 Supported JTAG Instruction ......................9-3...
Page 10: Logic Array Blocks And Adaptive Logic Modules In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 11: Mlab
CV-52001 MLAB 2014.01.10 Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V Devices This figure shows an overview of the Cyclone V LAB and MLAB structure with the LAB interconnects. C2/C4 Row Interconnects of Variable Speed and Length R3/R6...
Page 12: Local And Direct Link Interconnects
LAB’s local interconnect using the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Altera Corporation Send Feedback...
Page 13: Lab Control Signals
CV-52001 LAB Control Signals 2014.01.10 Figure 1-3: LAB Fast Local and Direct Link Interconnects for Cyclone V Devices Direct Link Interconnect from Direct Link Interconnect from Left LAB, Memory Block, Right LAB, Memory Block, DSP Block, or IOE Output DSP Block, or IOE Output...
Page 14: Alm Resources
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM. Note: The Quartus II software automatically configures the ALMs for optimized performance. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Altera Corporation Send Feedback...
Page 15: Alm Output
(LUT) of the same ALM so that the register is packed with its own fan-out LUT. The ALM can also drive out registered and unregistered versions of the LUT or adder output. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Altera Corporation...
Page 16: Alm Operating Modes
CV-52001 ALM Operating Modes 2014.01.10 Figure 1-6: ALM Connection Details for Cyclone V Devices ALM Operating Modes The Cyclone V ALM operates in any of the following modes: Normal mode Extended LUT mode Arithmetic mode Shared arithmetic mode Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...
Page 17: Normal Mode
2014.01.10 Normal Mode Normal mode allows two functions to be implemented in one Cyclone V ALM, or a single function of up to six inputs. Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
Page 18: Shared Arithmetic Mode
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. The two-bit carry select feature in Cyclone V devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.
Page 19 CV-52001 1-10 Shared Arithmetic Mode 2014.01.10 Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devices shared_arith_in carry_in labclk 4-Input datae0 4-Input reg0 datac datab dataa reg1 To General or 4-Input Local Routing datad datae1 reg2 4-Input shared_arith_out reg3...
Page 20: Document Revision History
Reorganized content and updated template. June 2012 Updated for the Quartus II software v12.0 release: Restructured chapter. Updated Figure 1–6. November 2011 Minor text edits. October 2011 Initial release. Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Altera Corporation Send Feedback...
Page 21: Embedded Memory Blocks In Cyclone V Devices
FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs). In the Cyclone V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Page 22: Embedded Memory Design Guidelines For Cyclone V Devices
CV-52002 Embedded Memory Design Guidelines for Cyclone V Devices 2013.05.06 M10K MLAB Member Variant Code Block RAM Bit (Kb) Block RAM Bit (Kb) Total RAM Bit (Kb) 1,190 1,349 2,500 2,795 Cyclone V GX 4,460 4,884 6,860 1338 7,696 1,220...
Page 23: Guideline: Implement External Conflict Resolution
The new data is available on the rising edge of the same clock cycle on which the new data is (flow-through) written. "don't care" M10K, MLAB The RAM outputs "don't care" values for a read-during-write operation. Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 24 Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time option. Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 25 This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “old data” mode. clk_a&b wren_a address_a data_a AAAA BBBB CCCC DDDD EEEE FFFF byteena_a rden_b address_b q_b (asynch) A0 (old data) AAAA BBBB A1 (old data) DDDD EEEE Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 26: Guideline: Consider Power-Up State And Memory Initialization
Bypassed Zero (cleared) By default, the Quartus II software initializes the RAM cells in Cyclone V devices to zero unless you specify a .mif. All memory blocks support initialization with a .mif. You can create .mif files in the Quartus II software and specify their use with the RAM megafunction when you instantiate a memory in your design.
Page 27: Guideline: Control Clocking To Reduce Power Consumption
Use the Quartus II software to automatically place any unused memory blocks in low-power mode to reduce static power. Embedded Memory Features Table 2-5: Memory Features in Cyclone V Devices This table summarizes the features supported by the embedded memory blocks. Features...
Page 28: Embedded Memory Configurations
Provides more information about the embedded memory features. Embedded Memory Configurations Table 2-6: Supported Embedded Memory Block Configurations for Cyclone V Devices This table lists the maximum configurations supported for the embedded memory blocks. The information is applicable only to the single-port RAM and ROM modes.
Page 29: Mixed-Width Port Configurations
— 2K x 5 — — — — — 1K x 8 — — — 1K x 10 — — — — — 512 x 16 — — — Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 30: Embedded Memory Modes
RAM, simple dual-port RAM, true dual-port RAM, or ROM mode. Table 2-9: Memory Modes Supported in the Embedded Memory Blocks This table lists and describes the memory modes that are supported in the Cyclone V embedded memory blocks. M10K...
Page 31: Embedded Memory Clocking Modes
Provides more information about implementing FIFO buffers. Embedded Memory Clocking Modes This section describes the clocking modes for the Cyclone V memory blocks. Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the memory block input registers during read or write operations.
Page 32: Asynchronous Clears In Clocking Modes
If you require the output read data to be a known value, use single-clock or ™ input/output clock mode and select the appropriate read-during-write behavior in the MegaWizard Plug- In Manager. Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 33: Independent Clock Enables In Clocking Modes
The byte enables are active high. Byte Enable Controls in Memory Blocks Table 2-12: Controls in x20 Data Width byteena byteena[1:0] Data Bits Written 11 (default) [19:10] [9:0] Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 34: Data Byte Output
“don't care” value or the current data at that location. You can control the output value for the masked byte in the MLABs by using the Quartus II software. Embedded Memory Blocks in Cyclone V Devices Altera Corporation...
Page 35: Ram Blocks Operations
). When the memory blocks are configured in dual-port addressstall = 1 mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled). Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 36 This figure shows the address clock enable waveform during the read cycle. inclock rdaddress rden addressstall latched address (inside memory) q (synch) doutn-1 doutn dout0 dout1 dout4 doutn dout0 dout1 dout4 q (asynch) dout5 Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 37: Document Revision History
ROM mode. Removed the topic about mixed-width configurations for MLABs and added a note to clarify that MLABs do not support mixed-width configuration. Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 38 Updated the “Memory Modes”, “Clocking Modes”, and “Design Considerations” sections. Updated Table 2–1. Added the “Parity Bit” and “Byte Enable” sections. Moved the memory capacity information to the Cyclone V Device Overview. October 2011 Initial release. Embedded Memory Blocks in Cyclone V Devices...
Page 39: Variable Precision Dsp Blocks In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 40: Supported Operational Modes In Cyclone V Devices
CV-52003 Supported Operational Modes in Cyclone V Devices 2014.01.10 Supported Operational Modes in Cyclone V Devices Table 3-1: Variable Precision DSP Blocks Operational Modes for Cyclone V Devices Input Variable-Precision Supported Pre-Adder Coefficient Operation Mode Cascade Chainout Support DSP Block Resource...
Page 41: Resources
CV-52003 Resources 2014.01.10 Resources Table 3-2: Number of Multipliers in Cyclone V Devices The table lists the variable-precision DSP resources by bit precision for each Cyclone V device. Independent Input and Output 18 x 18 18 x 18 Variable- Multiplications Operator...
Page 42: Design Considerations
After entering the parameter settings with the MegaWizard Plug-In Manager, the Quartus II software automatically configures the variable precision DSP block. Altera provides two methods for implementing various modes of the Cyclone V variable precision DSP block in a design—using the Quartus II DSP megafunction and HDL inferring.
Page 43: Block Architecture
CV-52003 Block Architecture 2014.01.10 Block Architecture The Cyclone V variable precision DSP block consists of the following elements: Input register bank Pre-adder Internal coefficient Multipliers Adder Accumulator and chainout adder Systolic registers Double accumulation register Output register bank If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.
Page 44: Input Register Bank
The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in 18 x 19 mode and dataa_y0 only in 27 x 27 mode, from the general routing or cascade chain. Variable Precision DSP Blocks in Cyclone V Devices Altera Corporation...
Page 45 CV-52003 Input Register Bank 2014.01.10 Figure 3-2: Input Register of a Variable Precision DSP Block in 18 x 19 Mode for Cyclone V Devices The figures show the data registers only. Registers for the control signals are not shown. CLK[2..0] ENA[2..0]...
Page 46: Pre-Adder
CV-52003 Pre-Adder 2014.01.10 Figure 3-3: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Cyclone V Devices The figures show the data registers only. Registers for the control signals are not shown. CLK[2..0] ENA[2..0] scanin[26..0] ACLR[0] dataa_y0[26..0]...
Page 47: Adder
Three 9 x 9 modes—you can use the adder as three 18-bit adders to produce three 9 x 9 multiplication results independently Accumulator and Chainout Adder The Cyclone V variable precision DSP block supports a 64-bit accumulator and a 64-bit adder. The following signals can dynamically control the function of the accumulator: NEGATE...
Page 48: Systolic Registers
CLK[2..0] ENA[2..0] ACLR[1] Operational Mode Descriptions This section describes how you can configure an Cyclone V variable precision DSP block to efficiently support the following operational modes: Independent Multiplier Mode Variable Precision DSP Blocks in Cyclone V Devices Altera Corporation...
Page 49: Independent Multiplier Mode
20 x 24 27 x 27 9 x 9 Independent Multiplier Figure 3-4: Three 9 x 9 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices Three pairs of data are packed into the ports; contains three 18-bit products.
Page 50 18 x 25 Independent Multiplier Figure 3-6: One 18 x 25 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices In this mode, the can be up to 52 bits when combined with a chainout adder or accumulator.
Page 51: Independent Complex Multiplier Mode
2014.01.10 20 x 24 Independent Multiplier Figure 3-7: One 20 x 24 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices In this mode, the can be up to 52 bits when combined with a chainout adder or accumulator.
Page 52 CV-52003 3-14 18 x 19 Complex Multiplier 2014.01.10 18 x 19 Complex Multiplier Figure 3-10: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Cyclone V Devices Variable-Precision DSP Block 1 Multiplier c[18..0] Adder b[17..0] Imaginary Part...
Page 53: Multiplier Adder Sum Mode
CV-52003 3-15 Multiplier Adder Sum Mode 2014.01.10 Multiplier Adder Sum Mode Figure 3-11: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Cyclone V Devices Variable-Precision DSP Block SUB_COMPLEX Multiplier dataa_y0[18..0] Chainout adder or accumulator dataa_x0[17..0]...
Page 54 [ 1 n [ 1 n 1 − Cyclone V variable precision DSP blocks support the following systolic FIR structures: 18-bit 27-bit In systolic FIR mode, the input of the multiplier can come from four different sets of sources:...
Page 55 CV-52003 3-17 27-Bit Systolic FIR Mode 2014.01.10 Figure 3-15: 18-Bit Systolic FIR Mode for Cyclone V Devices chainin[43..0] Systolic Multiplier Pre-Adder Register (1) dataa_y0[17..0] Systolic Registers (1) dataa_z0[17..0] dataa_x0[17..0] COEFSELA[2..0] Internal Adder Chainout adder or Coefficient accumulator Multiplier Pre-Adder datab_y1[17..0] datab_z1[17..0]...
Page 56: Document Revision History
18 x 18 multiplier adder summed with 36 bit input for Cyclone V SE A4 from 58 to 84. Corrected 18 x 18 multiplier for Cyclone V SE A4 from 116 to 168. Corrected 9 x 9 multiplier for Cyclone V SE A4 from 174 to 252.
Page 57 Register” sections. Updated Figure 3–1 and Figure 3–13. Added Table 3–3. Updated “Systolic Registers” and “Systolic FIR Mode” sections. Added Equation 3–2. Added Figure 3–12. May 2011 Initial release. Variable Precision DSP Blocks in Cyclone V Devices Altera Corporation Send Feedback...
Page 58: Clock Networks And Plls In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 59: Clock Resources In Cyclone V Devices
CV-52004 Clock Resources in Cyclone V Devices 2014.01.10 Clock Resources in Cyclone V Devices Table 4-1: Clock Resources in Cyclone V Devices Number of Resources Clock Resource Device Source of Clock Resource Available Cyclone V E A5, A7, and A9...
Page 60: Types Of Clock Networks
Types of Clock Networks Global Clock Networks Cyclone V devices provide GCLKs that can drive throughout the device. The GCLKs serve as low-skew clock sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP), embedded memory, and PLLs. Cyclone V I/O elements (IOEs) and internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out control signals, such as synchronous or asynchronous clear and clock enable signals.
Page 61 RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock insertion delay and skew for logic contained within a single device quadrant. The Cyclone V IOEs and Clock Networks and PLLs in Cyclone V Devices...
Page 62 RCLKs to create internally generated regional clocks and other high fan-out control signals. Figure 4-3: RCLK Networks in Cyclone V E, GX, and GT Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 63 PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Cyclone V device. Figure 4-5: PCLK Networks in Cyclone V E, GX, and GT Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 64: Clock Sources Per Quadrant
Clock Sources Per Quadrant The Cyclone V devices provide 30 section clock (SCLK) networks in each spine clock per quadrant. The SCLK networks can drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and two core reference clocks.
Page 65: Types Of Clock Regions
RCLK region. Internal logic can also drive a dual-regional clock network. Dual-regional clock region is only supported for quadrant 3 and quadrant 4 in Cyclone V SE, SX, and ST devices. Clock Networks and PLLs in Cyclone V Devices...
Page 66: Clock Network Sources
Clock Network Sources In Cyclone V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, and internal logic can drive the GCLK, RCLK, and PCLK networks. Dedicated Clock Input Pins You can use the dedicated clock input pins for high fan-out control signals, such as (CLK[0..11][p,n])
Page 67 CLK[6] This applies to all Cyclone V SE, SX, and ST devices except for Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4 devices. This applies to all Cyclone V E, GX, and GT devices except for Cyclone V E A2 and A4 devices, and Cyclone V GX C3 device.
Page 68: Clock Output Connections
RCLK[3,7,13,17,40,41,42,43,44,45,46,47,48,49,50,51,67,85] CLK[11] Table 4-5: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V SE, SX, and ST Devices A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network. Clock Resources...
Page 69 Pin Mapping in Cyclone V Devices Table 4-6: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs Clock Fed by Any of the four dedicated clock pins on the same side of the Cyclone V inclk[0] inclk[1] device.
Page 70 Provides more information about ALTCLKCTRL megafunction. PCLK Control Block To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic . Figure 4-11: Horizontal PCLK Control Block for Cyclone V Devices HSSI Output Internal Logic Static Clock Select...
Page 71: Clock Power Down
CV-52004 4-14 Clock Power Down 2014.01.10 Figure 4-12: External PLL Output Clock Control Block for Cyclone V Devices PLL Counter Outputs Static Clock Select When the device is in user mode, Enable/ you can only set the clock select Disable...
Page 72 (ena Port Registered as Double Register with Input Clock) Cyclone V devices have an additional metastability register that aids in asynchronous enable and disable of the GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.
Page 73: Cyclone V Plls
The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Cyclone V device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
Page 74: Pll Locations In Cyclone V Devices
Physical Counter C0 PLL Locations in Cyclone V Devices Cyclone V devices provide a PLL for each group of three transceiver channels. These PLLs are located in a strip, where the strip refers to an area in the FPGA. For the PLL in the strip, only PLL counter of the strip fractional PLLs are used in a clock network.
Page 75 Pins CLK[0..3][p,n] Figure 4-18: PLL Locations for Cyclone V E A5 Device, Cyclone V GX C4 and C5 Devices, and Cyclone V GT D5 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 76 2014.01.10 Figure 4-19: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, and Cyclone V GT D7 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 77 2014.01.10 Figure 4-20: PLL Locations for Cyclone V E A9 Device, Cyclone V GX C9 Device, and Cyclone V GT D9 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 78 2014.01.10 Figure 4-21: PLL Locations for Cyclone V SE A2 and A4 Devices, and Cyclone V SX C2 and C4 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Page 79: Pll Migration Guidelines
PLL Migration Guidelines If you plan to migrate your design between Cyclone V SX C2, C4, C5, and C6 devices, and your design requires a PLL to drive the HSSI and clock network (GCLK or RCLK), use the PLLs on the left side of the device.
Page 80: Pll Cascading
PLL External Clock I/O Pins All Cyclone V external clock outputs for corner fractional PLLs (that are not from the PLL strips) are dual- purpose clock I/O pins. Two external clock output pins associated with each corner fractional PLL are...
Page 81: Pll Control Signals
Differential SSTL Cyclone V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not require external PLL clocking.
Page 82: Clock Feedback Modes
PLL. However, if the PLL input is fed by a non-dedicated input (using the GCLK network), the output clock may not be perfectly aligned with the input clock. Clock Networks and PLLs in Cyclone V Devices Altera Corporation...
Page 83 Data pin to the IOE register input Clock input pin to the PLL phase frequency detector (PFD) input The Cyclone V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.
Page 84 The Quartus II TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the GCLK or RCLK network is fully compensated. Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 85 In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. This mode is supported on all Cyclone V PLLs. When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins.
Page 86 CV-52004 4-29 External Feedback Mode 2014.01.10 Figure 4-29: ZDB Mode in Cyclone V PLLs fbout EXTCLKOUT[0] FPLL_<#>_FB fbin EXTCLKOUT[1] Multiplexer inclk ÷N CP/LF Figure 4-30: Example of Phase Relationship Between the PLL Clocks in ZDB Mode Phase Aligned PLL Reference...
Page 87 When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs. This mode is supported only on the corner fractional PLLs. For Cyclone V E A2 and A4 devices, and Cyclone V GX C3 device, EFB mode is supported only on the left corner fractional PLLs.
Page 88: Clock Multiplication And Division
Provides more information about PLL clock outputs. Clock Multiplication and Division Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, , and is then multiplied by the feedback factor.
Page 89: Programmable Phase Shift
The following clock switchover modes are supported in Cyclone V PLLs: Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to clock.
Page 90 If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the signals are not valid. If both clock inputs are not the same frequency, but their period clkbad[0..1] Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 91 VCO operates within the recommended operating frequency range. The ALTERA_PLL MegaWizard Plug-in Manager notifies you if a given combination of frequencies cannot meet this requirement. inclk0 inclk1 Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 92 Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 93 Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide Provides more information about PLL software support in the Quartus II software. Guidelines When implementing clock switchover in Cyclone V PLLs, use the following guidelines: Automatic clock switchover requires that the frequencies be within 20% of each...
Page 94: Pll Reconfiguration And Dynamic Phase Shift
PLL Reconfiguration and Dynamic Phase Shift For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661. Related Information AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 95: Document Revision History
Cyclone V GT D7 device Added the following PLL locations diagrams: Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4 devices Cyclone V SE A5 and A6 devices, Cyclone V SX C5 and C6 devices, and Cyclone V ST D5 and D6 devices Added information on PLL migration guidelines.
Page 96 Updated diagrams for GCLK, RCLK, and PCLK networks. Updated diagram for clock sources per quadrant. Updated dual-regional clock region for Cyclone V SoC devices support. Restructured and updated tables for clock input pin connectivity to the GCLK and RCLK networks.
Page 97 Connections”, “Clock Enable Signals”, “PLL Control Signals”, “Clock Multiplication and Division”, “Programmable Duty Cycle”, “Clock Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift” sections. February 2012 Updated Table 4–2. October 2011 Initial release. Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback...
Page 98: I/O Features In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 99 CV-52005 I/O Resources Per Package for Cyclone V Devices 2014.01.10 Table 5-1: Package Plan for Cyclone V E Devices M383 M484 U324 F256 U484 F484 F672 F896 Member Code GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO — — —...
Page 100 I/O Resources Per Package for Cyclone V Devices 2014.01.10 Table 5-5: Package Plan for Cyclone V SX Devices The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA.
Page 101: I/O Vertical Migration For Cyclone V Devices
2014.01.10 I/O Vertical Migration for Cyclone V Devices Figure 5-1: Vertical Migration Capability Across Cyclone V Device Packages and Densities The arrows indicate the vertical migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.
Page 102: Verifying Pin Migration Compatibility
I/O Standards Support in Cyclone V Devices This section lists the I/O standards supported in the FPGA I/Os and HPS I/Os of Cyclone V devices, the typical power supply values for each I/O standard, and the MultiVolt I/O interface feature.
Page 103 CV-52005 I/O Standards Support for FPGA I/O in Cyclone V Devices 2014.01.10 I/O Standard Standard Support 3.0 V LVTTL/3.0 V LVCMOS JESD8-B 3.0 V PCI PCI Rev. 2.2 3.0 V PCI-X PCI-X Rev. 1.0 2.5 V LVCMOS JESD8-5 1.8 V LVCMOS JESD8-7 1.5 V LVCMOS...
Page 104: I/O Standards Support For Hps I/O In Cyclone V Devices
1.5 V HSTL Class II JESD8-6 — The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks. (10) The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true LVDS output buffer types on all I/O banks.
Page 105: I/O Standards Voltage Levels In Cyclone V Devices
HSUL-12 — — I/O Standards Voltage Levels in Cyclone V Devices Table 5-9: Cyclone V I/O Standards Voltage Levels This table lists the typical power supplies for each supported I/O standards in Cyclone V devices. CCIO CCPD I/O Standard (Pre-Driver...
Page 106 CV-52005 I/O Standards Voltage Levels in Cyclone V Devices 2014.01.10 CCIO CCPD I/O Standard (Pre-Driver (Input Ref (Board Termination (11) Input Output Voltage) Voltage) Voltage) Differential SSTL-2 Class — 1.25 CCPD Differential SSTL-2 Class — 1.25 CCPD Differential SSTL-18 Class —...
Page 107: Multivolt I/O Interface In Cyclone V Devices
Non-Voltage-Referenced I/O Standards on page 5-11 MultiVolt I/O Interface in Cyclone V Devices The MultiVolt I/O interface feature allows Cyclone V devices in all packages to interface with systems of different supply voltages. Table 5-10: MultiVolt I/O Support in Cyclone V Devices...
Page 108: I/O Design Guidelines For Cyclone V Devices
Note: If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O pins. Related Information...
Page 109: Plls And Clocking
PLLs and Clocking The Cyclone V device family supports fractional PLLs on each side of the device. You can use fractional PLLs to reduce the number of oscillators and the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source.
Page 110 Both corner PLLs can drive duplex channels in the same I/O bank if the channels that are driven by each PLL are not interleaved. You do not require separation between the groups of channels that are driven by both corner PLLs. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 111 Diff I/O Diff I/O Diff I/O Diff I/O Diff I/O Diff I/O Diff I/O Reference CLK Corner PLL Related Information Clock Networks and PLLs in Cyclone V Devices on page 4-1 I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 112: Lvds Interface With External Pll Mode
LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter instantiation when the external PLL option is enabled. Note: With soft SERDES, a different clocking requirement is needed. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 113 Note: For other clock and data phase relationships, Altera recommends that you first instantiate your ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option. Compile the megafunctions in the Quartus II software and take note of the frequency, phase shift, and duty cycle settings for each clock output.
Page 114: Guideline: Use The Same V
Guideline: Use the Same V for All I/O Banks in a Group CCPD In the Cyclone V devices, all I/O banks have individual V except the following I/O bank groups, which CCPD share V in each group:...
Page 115: Guideline: Ensure Compatible V
V Voltage in the Same Bank CCIO CCPD When planning I/O bank usage for Cyclone V devices, you must ensure the V voltage is compatible CCIO with the V voltage of the same bank. Some banks may share the same V power pin.
Page 116: Guideline: Adhere To The Lvds I/O Restrictions And Differential Pad Placement Rules
Receiver Application If you use the Cyclone V device as a receiver, use the on-chip clamping diode to limit the overshoot and undershoot voltage at the I/O pins.
Page 117 Figure 5-6: I/0 Banks for Cyclone V E Devices Bank 8A Bank 7A Bank 3A Bank 3B Bank 4A Figure 5-7: I/0 Banks for Cyclone V GX and GT Devices Bank 8A Bank 7A Bank 3A Bank 3B Bank 4A...
Page 118: I/O Banks Groups In Cyclone V Devices
5-27 I/O Banks Groups in Cyclone V Devices The I/O pins in Cyclone V devices are arranged in groups called modular I/O banks: Modular I/O banks have independent power supplies that allow each bank to support different I/O standards.
Page 119: Modular I/O Banks For Cyclone V E Devices
F256 U484 F484 — — — — — — — — Bank Total Table 5-15: Modular I/O Banks for Cyclone V E A5, A7, and A9 Devices Member Code Package M383 U484 F484 M484 U484 F484 F672 F896 U484 F484...
Page 120: Modular I/O Banks For Cyclone V Gx Devices
CV-52005 5-23 Modular I/O Banks for Cyclone V GX Devices 2014.01.10 Modular I/O Banks for Cyclone V GX Devices Table 5-16: Modular I/O Banks for Cyclone V GX C3, C4, and C5 Devices Member Code Package U324 U484 F484 M301...
Page 121: Modular I/O Banks For Cyclone V Gt Devices
CV-52005 5-24 Modular I/O Banks for Cyclone V GT Devices 2014.01.10 Modular I/O Banks for Cyclone V GT Devices Table 5-18: Modular I/O Banks for Cyclone V GT D5 and D7 Devices Member Code Package M301 M383 U484 F484 F672...
Page 122: Modular I/O Banks For Cyclone V Se Devices
Modular I/O Banks for Cyclone V SE Devices 2014.01.10 Modular I/O Banks for Cyclone V SE Devices Table 5-20: Modular I/O Banks for Cyclone V SE Devices Note: The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPS- specific pin may be mapped to several HPS I/Os.
Page 123: Modular I/O Banks For Cyclone V Sx Devices
Modular I/O Banks for Cyclone V SX Devices 2014.01.10 Modular I/O Banks for Cyclone V SX Devices Table 5-21: Modular I/O Banks for Cyclone V SX Devices Note: The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPS- specific pin may be mapped to several HPS I/Os.
Page 124: Modular I/O Banks For Cyclone V St Devices
CCPD I/O Element Structure in Cyclone V Devices The I/O elements (IOEs) in Cyclone V devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
Page 125 (PVT) variations. Figure 5-10: IOE Structure for Cyclone V Devices This figure shows the Cyclone V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT) control is available for each DQ/DQS group. From Core...
Page 126: Programmable Ioe Features In Cyclone V Devices
On, Off Recommended to turn on for 3.3 V I/O standards Note: The on-chip clamp diode is available on all general purpose I/O (GPIO) pins in all Cyclone V device variants. Related Information Cyclone V Device Datasheet Programmable Current Strength...
Page 127: Programmable Current Strength
Table 5-25: Programmable Current Strength Settings for Cyclone V Devices The output buffer for each Cyclone V device I/O pin has a programmable current strength control for the I/O standards listed in this table.
Page 128: Programmable Output Slew-Rate Control
You can specify the slew-rate on a pin-by-pin basis because each I/O pin contains a slew-rate control. Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application. Related Information...
Page 129: Programmable Pre-Emphasis
Programmable Pre-emphasis Allowed values 0 (disabled) and 1 (enabled) Related Information Programmable IOE Features in Cyclone V Devices on page 5-29 Programmable Differential Output Voltage The programmable V settings allow you to adjust the output eye opening to optimize the trace length and power consumption.
Page 130: I/O Pins Features For Cyclone V Devices
CV-52005 5-33 I/O Pins Features for Cyclone V Devices 2014.01.10 Figure 5-12: Differential V This figure shows the V of the differential LVDS output. Single-Ended Waveform Positive Channel (p) Negative Channel (n) Ground Differential Waveform (diff peak - peak) = 2 x V...
Page 131: Pull-Up Resistor
OCT provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs. The Cyclone V devices support OCT in all FPGA I/O banks. For the HPS I/Os, the column I/Os do not support OCT.
Page 132 CV-52005 5-35 OCT without Calibration in Cyclone V Devices 2014.01.10 Dynamic OCT in Cyclone V Devices on page 5-40 OCT without Calibration in Cyclone V Devices The Cyclone V devices support R OCT for single-ended and voltage-referenced I/O standards. R without calibration is supported on output only.
Page 133 CV-52005 5-36 OCT with Calibration in Cyclone V Devices 2014.01.10 Uncalibrated OCT (Output) I/O Standard (Ω) Differential 1.5 V HSTL Class II Differential 1.2 V HSTL Class I Differential 1.2 V HSTL Class II SSTL-15 25, 50, 34, 40 SSTL-135...
Page 134 CV-52005 5-37 OCT with Calibration in Cyclone V Devices 2014.01.10 Table 5-30: Selectable I/O Standards for R OCT With Calibration This table lists the output termination settings for calibrated OCT on different I/O standards. Calibrated OCT (Output) I/O Standard (12) (Ω)
Page 135 CV-52005 5-38 OCT with Calibration in Cyclone V Devices 2014.01.10 Calibrated OCT (Output) I/O Standard (12) (Ω) (Ω) 25, 50 SSTL-15 34, 40 SSTL-135 34, 40 SSTL-125 34, 40 HSUL-12 34, 40, 48, 60, 80 25, 50 Differential SSTL-15 34, 40...
Page 136 CV-52005 5-39 OCT with Calibration in Cyclone V Devices 2014.01.10 Table 5-31: Selectable I/O Standards for R OCT With Calibration This table lists the input termination settings for calibrated OCT on different I/O standards. Calibrated OCT (Input) I/O Standard (13) (Ω)
Page 137: Dynamic Oct In Cyclone V Devices
If you use the SSTL-15, SSTL-135, and SSTL-125 I/O standards with the DDR3 memory interface, Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic OCT reduces the number of external termination resistors used.
Page 138: Lvds Input R Doct In Cyclone V Devices
OCT if you set the V to 2.5 V. CCPD Figure 5-17: Differential Input OCT The Cyclone V devices support OCT for differential LVDS and SLVS input buffers with a nominal resistance value of 100 Ω, as shown in this figure. Transmitter Receiver = 50 Ω...
Page 139: Oct Calibration Block In Cyclone V Devices
CV-52005 5-42 OCT Calibration Block in Cyclone V Devices 2014.01.10 OCT Calibration Block in Cyclone V Devices You can calibrate the OCT using any of the available four OCT calibration blocks for each device. Each calibration block contains one pin.
Page 140 OCT calibration codes from the OCT calibration block in bank 3A to the I/O banks around the periphery. Related Information Sharing an OCT Calibration Block on Multiple I/O Banks on page 5-42 I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 141: External I/O Termination For Cyclone V Devices
CV-52005 5-44 External I/O Termination for Cyclone V Devices 2014.01.10 Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide Provides more information about the OCT calibration block. External I/O Termination for Cyclone V Devices Table 5-33: External Termination Schemes for Different I/O Standards...
Page 142: Single-Ended I/O Termination
OCT simultaneously. For more information, refer to the related information. (14) Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic OCT reduces the number of external termination resistors used. I/O Features in Cyclone V Devices...
Page 143 CV-52005 5-46 Single-ended I/O Termination 2014.01.10 Figure 5-20: SSTL I/O Standard Termination This figure shows the details of SSTL I/O termination on Cyclone V devices. Termination SSTL Class I SSTL Class II 50 Ω 50 Ω 50 Ω 25 Ω...
Page 144: Differential I/O Termination
The supported I/O standards such as Differential SSTL-15, Differential SSTL-125, and Differential SSTL- 135 typically do not require external board termination. Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic OCT reduces the number of external termination resistors used.
Page 145 100 Ω Transmitter Receiver Transmitter Receiver Figure 5-23: Differential HSTL I/O Standard Termination This figure shows the details of Differential HSTL I/O standard termination on Cyclone V devices. Termination Differential HSTL Class I Differential HSTL Class II 50 Ω 50 Ω...
Page 146 The I/O banks also support emulated LVDS, RSDS, and mini-LVDS I/O standards. Emulated LVDS, RSDS and mini-LVDS output buffers use two single-ended output buffers with an external single-resistor or three-resistor network, and can be tri-stated. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 147 Output with Three-Resistor 100 Ω Network, LVDS_E_3R) 50 Ω External Resistor Receiver Transmitter To meet the RSDS or mini-LVDS specifications, you require a resistor network to attenuate the output- voltage swing. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 148 For more information about the RSDS I/O standard, refer to the RSDS Specification on the National Semiconductor web site. LVPECL Termination The Cyclone V devices support the LVPECL I/O standard on input clock pins only: LVPECL input operation is supported using LVDS input buffers. LVPECL output operation is not supported.
Page 149: Dedicated High-Speed Circuitries
Related Information Cyclone V Device Datasheet Dedicated High-Speed Circuitries The Cyclone V device has dedicated circuitries for differential transmitter and receiver to transmit or receive high-speed differential signals. Table 5-34: Features and Dedicated Circuitries of the Differential Transmitter and Receiver...
Page 150: High-Speed Differential I/O Locations
Embedded Memory, Transceiver Block Clock Networks) Figure 5-31: High-Speed Differential I/O Locations in Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices General Purpose I/O and High-Speed LVDS I/O with SERDES...
Page 151: Lvds Serdes Circuitry
(Logic Elements, DSP, Embedded Memory, Clock Networks) Figure 5-33: High-Speed Differential I/O Locations in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices General Purpose I/O and High-Speed LVDS I/O with SERDES...
Page 152: True Lvds Buffers In Cyclone V Devices
SERDES. Note: True LVDS output buffers cannot be tri-stated. The following tables list the number of true LVDS buffers supported in Cyclone V devices with these conditions: The LVDS channel count does not include dedicated clock pins. I/O Features in Cyclone V Devices...
Page 153 Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are not interleaved. Table 5-35: LVDS Channels Supported in Cyclone V E Devices Member Code Package...
Page 154 CV-52005 5-57 True LVDS Buffers in Cyclone V Devices 2014.01.10 Member Code Package Side 484-pin Micro FineLine BGA Right Bottom 484-pin Ultra FineLine BGA Right Bottom 484-pin FineLine BGA Right Bottom 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right...
Page 155 CV-52005 5-58 True LVDS Buffers in Cyclone V Devices 2014.01.10 Table 5-36: LVDS Channels Supported in Cyclone V GX Devices Member Code Package Side 324-pin Ultra FineLine BGA Right Bottom 484-pin Ultra FineLine BGA Right Bottom 484-pin FineLine BGA Right...
Page 156 CV-52005 5-59 True LVDS Buffers in Cyclone V Devices 2014.01.10 Member Code Package Side 301-pin Micro FineLine BGA Right Bottom 383-pin Micro FineLine BGA Right Bottom 484-pin Ultra FineLine BGA Right Bottom 484-pin FineLine BGA Right Bottom 672-pin FineLine BGA...
Page 157 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right Bottom 1152-pin FineLine BGA Right Bottom Table 5-37: LVDS Channels Supported in Cyclone V GT Devices Member Code Package Side 301-pin Micro FineLine BGA Right Bottom 383-pin Micro FineLine BGA Right...
Page 158 CV-52005 5-61 True LVDS Buffers in Cyclone V Devices 2014.01.10 Member Code Package Side 484-pin Micro FineLine BGA Right Bottom 484-pin Ultra FineLine BGA Right Bottom 484-pin FineLine BGA Right Bottom 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right...
Page 159 CV-52005 5-62 True LVDS Buffers in Cyclone V Devices 2014.01.10 Table 5-38: LVDS Channels Supported in Cyclone V SE Devices Member Code Package Side 484-pin Ultra FineLine BGA Right Bottom A2 and A4 672-pin Ultra FineLine BGA Right Bottom 484-pin Ultra FineLine BGA...
Page 160: Emulated Lvds Buffers In Cyclone V Devices
The emulated differential output buffers support tri-state capability. Differential Transmitter in Cyclone V Devices The Cyclone V transmitter contains dedicated circuitry to support high-speed differential signaling. The differential transmitter buffers support the following features: LVDS signaling that can drive out LVDS, mini-LVDS, and RSDS signals...
Page 161: Serializer Bypass For Ddr And Sdr Operations
The load enable signal is derived from the serialization factor setting. You can configure any Cyclone V transmitter data channel to generate a source-synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.
Page 162: Differential Receiver In Cyclone V Devices
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-12 Receiver Blocks in Cyclone V Devices The Cyclone V differential receiver has the following hardware blocks: Data realignment block (bit slip) Deserializer The following figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Page 163 You can set the value of the bit rollover point using the MegaWizard Plug-In Manager. An optional status port, , is available to the FPGA RX_CDA_MAX fabric from each channel to indicate the reaching of the preset rollover point. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 164: Receiver Mode In Cyclone V Devices
IOE is 1 and 2 bits, respectively. Receiver Mode in Cyclone V Devices The Cyclone V devices support the LVDS receiver mode. LVDS Receiver Mode Input serial data is registered at the rising edge of the serial...
Page 165: Receiver Clocking For Cyclone V Devices
5-12 Differential I/O Termination for Cyclone V Devices The Cyclone V devices provide a 100 Ω, on-chip differential termination option on each differential receiver channel for LVDS standards. On-chip termination saves board space by eliminating the need to add external resistors on the board.
Page 166: Source-Synchronous Timing Budget
IC vendors and is strongly influenced by board skew, cable skew, and clock jitter. This section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for the Cyclone V device family, and how to use these timing parameters to determine the maximum performance of a design.
Page 167: Differential I/O Bit Position
This table lists the conventions for differential bit naming for 18 differential channels, and the bit positions after deserialization. Internal 8-Bit Parallel Data Receiver Channel Data Number MSB Position LSB Position I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 168: Transmitter Channel-To-Channel Skew
Transmitter Channel-to-Channel Skew The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an important parameter based on the Cyclone V transmitter in a source-synchronous differential interface: TCCS is the difference between the fastest and slowest data output transitions, including the T variation and clock skew.
Page 169 Input Data (min) Internal (max) Bit n Clock Bit n Falling Edge Timing Budget External Clock Clock Placement Internal Clock Synchronization Transmitter Output Data RSKM RSKM TCCS TCCS Receiver Input Data I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 170: Document Revision History
Removed SSTL-125 from the list of supported I/O standards for the HPS I/O. Added SSTL-15, SSTL-135, SSTL-125, HSUL-12, Differential SSTL-15, Differential SSTL-135, Differential SSTL-125, and Differential HSUL-12 to the list of output termination settings for uncalibrated R OCT. I/O Features in Cyclone V Devices Altera Corporation Send Feedback...
Page 171 Removed I/O banks 5A and 5B from Cyclone V SE A2 and A4, and Cyclone V SX C2 and C4 in the table that lists the reference clock pin for I/O banks without dedicated reference clock pin. These devices do not have I/O bank 5B.
Page 172 Cyclone V devices. Added Bank 1A to the I/O banks location figure for Cyclone V E devices because it is now available for the Cyclone V E A2 and A4 devices. Added the M383 and M484 packages to the modular I/O banks tables for Cyclone V E devices, and added the U484 package for the Cyclone V E A9 device.
Page 173 Added the M383 package to the Cyclone V E A2, A4 and A4, Cyclone V GX C5, and Cyclone V GT D5 devices. Added the M484 package to the Cyclone V E A7, Cyclone V GX C7, and Cyclone V GT D7 devices.
Page 174 Removed statements about LVDS SERDES being available on top and bottom banks only. Removed the topic about LVDS direct loopback mode. Updated the true LVDS buffers count for Cyclone V E, GX, and GT devices. Added the RSKM equation, description, and high-speed timing diagram.
Page 175: External Memory Interfaces In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 176: External Memory Performance
Memory Interface Pin Support in Cyclone V Devices In the Cyclone V devices, the memory interface circuitry is available in every I/O bank that does not support transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.
Page 177: Guideline: Using Dq/Dqs Pins
(R) side of the device. Note: The F484 package of the Cyclone V E A9, GX C9, and GT D9 devices can only support a 24 bit hard memory controller on the top side using the pin assignments. Even though the...
Page 178 DDR3 and DDR2 interfaces—each x8 group of pins require one DQS pin. You may also require one DQSn pin and one DM pin. This further reduces the total number of data pins available. Table 6-4: DQ/DQS Bus Mode Pins for Cyclone V Devices Data Mask...
Page 179: Dq/Dqs Groups In Cyclone V E
2014.01.10 DQ/DQS Groups in Cyclone V E Table 6-5: Number of DQ/DQS Groups Per Side in Cyclone V E Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device.
Page 180 484-pin FineLine BGA Right Bottom 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right Bottom Related Information Cyclone V Device Pin-Out Files Download the relevant pin tables from this web page. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 181: Dq/Dqs Groups In Cyclone V Gx
2014.01.10 DQ/DQS Groups in Cyclone V GX Table 6-6: Number of DQ/DQS Groups Per Side in Cyclone V GX Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device.
Page 182 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right Bottom 1152-pin FineLine BGA Right Bottom Related Information Cyclone V Device Pin-Out Files Download the relevant pin tables from this web page. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 183: Dq/Dqs Groups In Cyclone V Gt
2014.01.10 DQ/DQS Groups in Cyclone V GT Table 6-7: Number of DQ/DQS Groups Per Side in Cyclone V GT Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device.
Page 184 672-pin FineLine BGA Right Bottom 896-pin FineLine BGA Right Bottom 1152-pin FineLine BGA Right Bottom Related Information Cyclone V Device Pin-Out Files Download the relevant pin tables from this web page. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 185: Dq/Dqs Groups In Cyclone V Se
2014.01.10 DQ/DQS Groups in Cyclone V SE Table 6-8: Number of DQ/DQS Groups Per Side in Cyclone V SE Devices This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the DQ/DQS groups from the pin table of the specific device.
Page 186: Dq/Dqs Groups In Cyclone V St
The Cyclone V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency) to half rate (the controller frequency) and vice versa.
Page 187: External Memory Interface Datapath
Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements. DQS Phase-Shift Circuitry The Cyclone V DLL provides phase shift to the DQS pins on read transactions if the DQS pins are acting as input clocks or strobes to the FPGA.
Page 188 CV-52006 6-14 DQS Phase-Shift Circuitry 2014.01.10 Figure 6-2: DQS Pins and DLLs in Cyclone V E (A2 and A4) Devices DQS Logic Reference Reference Blocks Clock Clock Δt Δt Δt Δt DQS Logic DQS Logic Blocks Blocks Δt Δt Δt Δt...
Page 189 CV-52006 6-15 DQS Phase-Shift Circuitry 2014.01.10 Figure 6-3: DQS Pins and DLLs in Cyclone V GX (C3) Devices DQS Logic Reference Reference Blocks Clock Clock Δt Δt Δt Δt DQS Logic Blocks Δt Δt Δt Δt to IOE to IOE...
Page 190 CV-52006 6-16 DQS Phase-Shift Circuitry 2014.01.10 Figure 6-4: DQS Pins and DLLs in Cyclone V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, and D9) Devices DQS Logic Reference Blocks Reference Clock Clock Δt Δt...
Page 191 CV-52006 6-17 DQS Phase-Shift Circuitry 2014.01.10 Figure 6-5: DQS Pins and DLLs in Cyclone V SE (A2, A4, A5, and A6) Devices Reference Clock Δt Δt to IOE HPS I/O to IOE DQS Logic Blocks Δt to IOE HPS Block Δt...
Page 192 CV-52006 6-18 Delay-Locked Loop 2014.01.10 Figure 6-6: DQS Pins and DLLs in Cyclone V SX (C2, C4, C5, and C6) and ST (D5 and D6) Devices Reference Clock Δt Δt to IOE HPS I/O to IOE DQS Logic Blocks Δt...
Page 193 DLL Reference Clock Input for Cyclone V Devices Table 6-11: DLL Reference Clock Input from PLLs for Cyclone V E (A2, A4, A5, A7, and A9), GX (C4, C5, C7, and C9), and GT (D5, D7, and D9) Devices—Preliminary...
Page 194 IOE read FIFO for resynchronization. For Cyclone V SoC devices, you can feed the hard processor system (HPS) DQS delay settings to the HPS DQS logic block only.
Page 195: Phy Clock (Phyclk) Networks
The top and bottom sides of the Cyclone V devices have up to four PHYCLK networks each. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.
Page 196 I/O Bank 3 I/O Bank 4 Figure 6-10: PHYCLK Networks in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices I/O Bank 8...
Page 197 Sub-Bank Sub-Bank Sub-Bank Sub-Bank I/O Bank 3 I/O Bank 4 Figure 6-12: PHYCLK Networks in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices I/O Bank 8 I/O Bank 7 Sub-Bank Sub-Bank...
Page 198: Dqs Logic Block
Each DQS/CQ/CQn/QK# pin is connected to a separate DQS logic block, which consists of the update enable circuitry, DQS delay chains, and DQS postamble circuitry. The following figure shows the DQS logic block. Figure 6-13: DQS Logic Block in Cyclone V Devices DQS Delay Chain DQS Postamble Circuitry...
Page 199 The number of delay chains required is transparent because the UniPHY IP automatically sets it when you choose the operating frequency. In the Cyclone V SE, SX, and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry only.
Page 200: Dynamic Oct Control
The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip parallel termination (R OCT) on during a read and turn R OCT off during a write. Figure 6-16: Dynamic OCT Control Block for Cyclone V Devices OCT Control Path OCT Control OCT Enable...
Page 201 The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half rate. The following figure shows the registers available in the Cyclone V input path. For DDR3 and DDR2 SDRAM interfaces, the DQS and DQSn signals must be inverted. If you use Altera’s memory interface IPs, the DQS and DQSn signals are automatically inverted.
Page 202: Delay Chains
90° offset to the DQS write clock. Delay Chains The Cyclone V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks. You can control the delay chain setting through the I/O or the DQS configuration block output.
Page 203: I/O And Dqs Configuration Blocks
I/O and DQS Configuration Blocks The I/O and DQS configuration blocks are shift registers that you can use to dynamically change the settings of various device configuration bits. The shift registers power-up low. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 204: Hard Memory Controller
Provides details about the I/O and DQS configuration block bit sequence. Hard Memory Controller The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers for LPDDR2, DDR2, and DDR3 SDRAM interfaces. Compared to the memory controllers implemented using core logic, the hard memory controllers allow support for higher memory interface frequencies with shorter latency cycles.
Page 205 User-Controlled You can optionally control when refreshes occur—allowing the refreshes to avoid Refresh Timing clashing of important reads or writes with the refresh lock-out time. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 206: Multi-Port Front End
Figure 6-22: Simplified Diagram of the Cyclone V Hard Memory Interface This figure shows a simplified diagram of the Cyclone V hard memory interface with the MPFE. FPGA...
Page 207: Bonding Support
CV-52006 6-33 Numbers of MPFE Ports Per Device 2014.01.10 Numbers of MPFE Ports Per Device Table 6-15: Numbers of MPFE Command, Write-Data, and Read-Data Ports for Each Cyclone V Device MPFE Ports Variant Member Code Command Write-data Read-data Cyclone V E...
Page 208 Bonding Support 2014.01.10 Figure 6-23: Hard Memory Controllers Bonding Support in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices This figure shows the bonding of two opposite hard memory controllers through the core fabric.
Page 209: Hard Memory Controller Width For Cyclone V E
Hard Memory Controller Width for Cyclone V E 2014.01.10 Figure 6-24: Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices This figure shows hard memory controllers in the SoC devices. There is no bonding support.
Page 210: Hard Memory Controller Width For Cyclone V Gx
Important information about usable pin assignments for the hard memory controller in the F484 package of this device. Hard Memory Controller Width for Cyclone V GX Table 6-17: Hard Memory Controller Width Per Side in Cyclone V GX Devices—Preliminary Member Code Package...
Page 211: Hard Memory Controller Width For Cyclone V Gt
CV-52006 6-37 Hard Memory Controller Width for Cyclone V GT 2014.01.10 Hard Memory Controller Width for Cyclone V GT Table 6-18: Hard Memory Controller Width Per Side in Cyclone V GT Devices—Preliminary Member Code Package Bottom Bottom Bottom M301 —...
Page 212: Hard Memory Controller Width For Cyclone V Sx
CV-52006 6-38 Hard Memory Controller Width for Cyclone V SX 2014.01.10 Hard Memory Controller Width for Cyclone V SX Table 6-21: Hard Memory Controller Width Per Side in Cyclone V SX Devices—Preliminary Member Code Package Bottom Bottom Bottom Bottom U672 F896 —...
Page 213: Document Revision History
Updated the DQ/DQS numbers for the M383 package of Cyclone V E, GX, and GT variants. Removed the statement about the bottom hard memory controller restrictions in the figure that shows the Cyclone V GX C5 hard memory controller bonding. Added information about the hard memory controller interface widths for the Cyclone V SE.
Page 214 Cyclone V E, GX, and GT device. Added a note about the usable hard memory controller pin assignments for the F484 package of the Cyclone V E A9, GX C9, and GT D9 devices. Updated the M386 package to M383.
Page 215 Added SoC devices information. Added Figure 6–5, Figure 6–10, and Figure 6–21. February 2012 Updated Figure 6–20. Minor text edits. November 2011 Updated Table 6–2. Added Figure 6–2. October 2011 Initial release. External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback...
Page 216: Configuration, Design Security, And Remote System Upgrades In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 217: Msel Pin Settings
— — Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Page 218: Configuration Sequence
CV-52007 Configuration Sequence 2014.01.10 Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices Configuration Scheme Compression Design Security Power-On Reset Valid MSEL[4..0] CCPGM Feature Feature (POR) Delay Fast 10100 Disabled Disabled 1.8/2.5/3.0/3.3 Standard 11000 Fast 10101...
Page 219: Power Up
CCPGM The configuration input buffers do not have to share power lines with the regular I/O buffers in Cyclone V devices. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation...
Page 220: Configuration Error Handling
Provides more information about configuration pins. I/O Standards Voltage Levels in Cyclone V Devices on page 5-8 Provides more information about typical power supplies for each supported I/O standards in Cyclone V devices. Reset POR delay is the time frame between the time when all the power supplies monitored by the POR circuitry...
Page 221: Initialization
By default, the internal CLKUSR DCLK oscillator is the clock source for initialization. If you use the internal oscillator, the Cyclone V device will be provided with enough clock cycles for proper initialization. Note: If you use the optional...
Page 222 DATA4 Input — CCPGM Bidirectional — CCPGM AS_DATA[3..1] DATA[3..1] Input — CCPGM Bidirectional — CCPGM AS_DATA0 DATA0 ASDO FPP and PS Input — CCPGM Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 223: Configuration Pin Options In The Quartus Ii Software
V of the bank in which the pin CCPGM CCIO resides when you use this pin as a user I/O pin. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 224: Fast Passive Parallel Configuration
Provides more information about the FPP configuration timing. Fast Passive Parallel Single-Device Configuration To configure a Cyclone V device, connect the device to an external host as shown in the following figure. Figure 7-2: Single Device FPP Configuration Using an External Host...
Page 225: Fast Passive Parallel Multi-Device Configuration
Using Multiple Configuration Data To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to an external host as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices...
Page 226 Configuration automatically begins for the second device in one clock cycle. Using One Configuration Data To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an external host as shown in the following figure.
Page 227: Active Serial Configuration
Configuration page of the Quartus II software. After power-up, is driven by a 12.5 MHz internal oscillator by default. The Cyclone V device determines DCLK the clock source and frequency to use by reading the option bit in the programming file.
Page 228: Active Serial Single-Device Configuration
AS configuration scheme. DCLK Active Serial Single-Device Configuration To configure a Cyclone V device, connect the device to a serial configuration (EPCS) device or quad-serial configuration (EPCQ) device, as shown in the following figures. Figure 7-5: Single Device AS x1 Mode Configuration Connect the pull-up resistors to at 3.0- or 3.3-V power supply.
Page 229: Active Serial Multi-Device Configuration
2014.01.10 Active Serial Multi-Device Configuration You can configure multiple Cyclone V devices that are connected to a chain. Only AS x1 mode supports multi-device configuration. The first device in the chain is the configuration master. Subsequent devices in the chain are configuration slaves.
Page 230: Estimating The Active Serial Configuration Time
Compressing the configuration data reduces the configuration time. The amount of reduction varies depending on your design. Using EPCS and EPCQ Devices EPCS devices support AS x1 mode and EPCQ devices support AS x1 and AS x4 modes. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 231: Controlling Epcs And Epcq Devices
Trace Length and Loading The maximum trace length and loading apply to both single- and multi-device AS configuration setups as listed in the following table. The trace length is the length from the Cyclone V device to the EPCS or EPCQ device.
Page 232 10-pin header. Programming EPCQ Using the JTAG Interface To program an EPCQ device using the JTAG interface, connect the device as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 233 Programming EPCS Using the Active Serial Interface To program an EPCS device using the AS interface, connect the device as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 234 Programming EPCQ Using the Active Serial Interface To program an EPCQ device using the AS interface, connect the device as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 235: Passive Serial Configuration
When programming the EPCS and EPCQ devices, the download cable disables access to the AS interface by driving the pin high. The line is also pulled low to hold the Cyclone V device in the reset nCONFIG stage. After programming completes, the download cable releases...
Page 236: Passive Serial Single-Device Configuration Using An External Host
Cyclone V device. For a PC host, connect the PC to the device using a download cable such as the Altera USB-Blaster USB port, ByteBlaster II parallel port, EthernetBlaster, and EthernetBlaster II download cables.
Page 237: Passive Serial Multi-Device Configuration
Using Multiple Configuration Data To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to the external host as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices...
Page 238 Configuration automatically begins for the second device in one clock cycle. Using One Configuration Data To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an external host, as shown in the following figure.
Page 239: Jtag Configuration
Using PC Host and Download Cable To configure multiple Cyclone V devices, connect the devices to a download cable, as shown in the following figure. Figure 7-16: Multiple Device PS Configuration Using an Altera Download Cable...
Page 240: Jtag Single-Device Configuration
1,222 cycles to perform device initialization. To configure a Cyclone V device using a download cable, connect the device as shown in the following figure. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices...
Page 241 MSEL[4..0], nCONFIG, and DCLK based on the selected configuration scheme. To configure a Cyclone V device using a microprocessor, connect the device as shown in the following figure. You can use JRunner as your software driver. Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor...
Page 242: Jtag Multi-Device Configuration
, and pins with an on-board buffer. You can also connect other Altera devices with JTAG support to the chain. JTAG-chain device programming is ideal when the system contains multiple devices or when testing your system using the JTAG boundary-scan testing (BST) circuitry.
Page 243: Configuration Data Compression
6. Turn on the Compression check box. Using Compression in Multi-Device Configuration The following figure shows a chain of two Cyclone V devices. Compression is only enabled for the first device. This setup is supported by the AS or PS multi-device configuration only.
Page 244: Remote System Upgrades
The following list is the sequence of the remote system upgrade: 1. The logic (embedded processor or user logic) in the Cyclone V device receives a configuration image from a remote location. You can connect the device to the remote source using communication protocols such as TCP/IP, PCI, user datagram protocol (UDP), UART, or a proprietary interface.
Page 245: Configuration Images
2014.01.10 Configuration Images Each Cyclone V device in your system requires one factory image. The factory image is a user-defined configuration image that contains logic to perform the following: Processes errors based on the status provided by the dedicated remote system upgrade circuitry.
Page 246: Remote System Upgrade Circuitry
Enabling this feature automatically turns on the Auto-restart configuration after error option. Altera-provided ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Cyclone V device logic. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices...
Page 247: Remote System Upgrade Registers
This register is clocked by the 10-MHz internal oscillator. Related Information Control Register on page 7-33 Status Register on page 7-33 Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 248 This is the default value after the device exits POR and during reconfiguration back to the factory configuration image. (19) After the device exits POR and power-up, the status register content is 5'b00000. Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 249: Remote System Upgrade State Machine
Secure operation mode for both volatile and non-volatile key through tamper protection bit setting Limited accessible JTAG instruction during power-up in the JTAG secure mode Supports board-level testing Supports in-socket key programming for non-volatile key Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices Altera Corporation Send Feedback...
Page 250: Altchip_Id Megafunction
When you use compression with the design security feature, the configuration file is first compressed and then encrypted using the Quartus II software. During configuration, the device first decrypts and then decompresses the configuration file. When you use design security with Cyclone V devices in an FPP configuration scheme, it requires a different -to- ratio.
Page 251: Security Key Types
Provides more information about JTAG binary instruction code related to the LOCK UNLOCK instructions. Security Key Types Cyclone V devices offer two types of keys—volatile and non-volatile. The following table lists the differences between the volatile key and non-volatile keys. Table 7-9: Security Key Types Key Types Key Programmability...
Page 252: Security Modes
Note: For the volatile key with tamper protection bit set security mode, Cyclone V devices do not accept the encrypted configuration file if the volatile key is erased. If the volatile key is erased and you want to reprogram the key, you must use the volatile key security mode.
Page 253: Document Revision History
3. Program the AES key programming file into the Cyclone V device through a JTAG interface. 4. Configure the Cyclone V device. At the system power-up, the external memory device sends the encrypted configuration file to the Cyclone V device.
Page 254: Seu Mitigation For Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 255: Specifications
Using a lower clock frequency increases the interval time, hence increasing the time required to recover from a single event upset (SEU). Table 8-1: Estimated Minimum EMR Update Interval in Cyclone V Devices Variant Member Code Timing Interval (µs)
Page 256: Error Detection Frequency
Figure 8-1: Error Detection Frequency Equation Internal Oscillator Frequency Error Detection Frequency = Table 8-2: Error Detection Frequency Range for Cyclone V Devices The following table lists the frequencies and valid values of n. Error Detection Frequency Internal Oscillator Frequency...
Page 257: Using Error Detection Features In User Mode
Using Error Detection Features in User Mode 2013.11.12 Table 8-3: CRC Calculation Time in Cyclone V Devices The following table lists the minimum and maximum time taken to calculate the CRC value: The minimum time is derived using the maximum clock frequency with a divisor of 0.
Page 258: Crc_Error Pin
Error Message CRC_ERROR Register Error Injection Block JTAG User Fault Update Update Injection Register Register Register JTAG JTAG User Fault Shift Shift Injection Register Register Register JTAG TDO General Routing SEU Mitigation for Cyclone V Devices Altera Corporation Send Feedback...
Page 259 Figure 8-3: Error Message Register Map Double Word Syndrome Frame Address Byte Offset Bit Offset Error Type Location 32 bits 16 bits 10 bits 2 bits 3 bits 4 bits SEU Mitigation for Cyclone V Devices Altera Corporation Send Feedback...
Page 260: Error Detection Process
CRC calculation for a minimum of 32 clock cycles. When CRC_ERROR an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever SEU Mitigation for Cyclone V Devices Altera Corporation Send Feedback...
Page 261: Testing The Error Detection Block
8-2 Provides more information about the duration of each Cyclone Vdevice. Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices Provides more information about how to retrieve the error information. Testing the Error Detection Block You can inject errors into the configuration data to test the error detection block.
Page 262: Document Revision History
You can only inject errors into the first frame of the configuration data. However, you can monitor the error information at any time. Altera recommends that you reconfigure the FPGA after the test completes. Automating the Testing Process ™...
Page 263: Jtag Boundary-Scan Testing In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 264 CV-52009 IDCODE 2014.01.10 Table 9-1: IDCODE Information for Cyclone V Devices IDCODE (32 Bits) Version (4 Bits) Part Number Manufacture LSB (1 Bit) Variant Member Code (16 Bits) Identity (11 Bits) 0000 0010 1011 0001 000 0110 1110 0101 0000...
Page 265: Supported Jtag Instruction
0010 Cyclone V ST 0000 0010 1101 0000 000 0110 1110 0010 Supported JTAG Instruction Table 9-2: JTAG Instructions Supported by Cyclone V Devices JTAG Instruction Instruction Code Description 00 0000 0101 Allows you to capture and examine SAMPLE PRELOAD...
Page 266 IDCODE power up and in the TAP RESET state. Without loading any instruc- tions, you can go to the SHIFT_DR state and shift out the JTAG device JTAG Boundary-Scan Testing in Cyclone V Devices Altera Corporation Send Feedback...
Page 267 JTAG ports using I/O configuration shift register (IOCSR) for JTAG testing. You can issue the instruc- CONFIG_IO tion only after the pin goes nSTATUS high. JTAG Boundary-Scan Testing in Cyclone V Devices Altera Corporation Send Feedback...
Page 268: Jtag Secure Mode
PULSE_NCONFIG CONFIG_IO LOCK UNLOCK JTAG Secure Mode If you enable the tamper-protection bit, the Cyclone V device is in JTAG secure mode after power up. In the JTAG secure mode, the JTAG pins support only the BYPASS SAMPLE PRELOAD EXTEST...
Page 269: I/O Voltage For Jtag Operation
0011100101 0011100110 0000101010 0000101011 I/O Voltage for JTAG Operation The Cyclone V device operating in IEEE Std. 1149.1 BST mode uses four dedicated JTAG pins— , and . Cyclone V devices do not support the optional pin. TRST pin has an internal weak pull-down resistor, while the pins have internal weak pull-up resistors.
Page 270: Enabling And Disabling Ieee Std. 1149.1 Bst Circuitry
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry The IEEE Std. 1149.1 BST circuitry is enabled after the Cyclone V device powers up. However for Cyclone V SoC FPGAs, you must power up both HPS and FPGA to perform BST.
Page 271: Guidelines For Ieee Std. 1149.1 Boundary-Scan Testing
The boundary-scan register consists of 3-bit peripheral elements that are associated with Cyclone V I/O pins. You can use the boundary-scan register to test external pin connections or to capture internal data.
Page 272: Boundary-Scan Cells Of A Cyclone V Device I/O Pin
Internal Logic configuration pin. TAP Controller Boundary-Scan Cells of a Cyclone V Device I/O Pin The Cyclone V device 3-bit BSC consists of the following registers: Capture registers—Connect to internal device data through the , and signals. OUTJ PIN_IN Update registers—Connect to external data through the...
Page 273 BSCs. VREF Table 9-5: Boundary-Scan Cell Descriptions for Cyclone V Devices This table lists the capture and update register capabilities of all BSCs within Cyclone V devices. Captures Drives Output OE Capture...
Page 274: Document Revision History
Updated Table 9-1 and Table 9-2. October 2011 Initial release. (25) This includes the pins. CONF_DONE nSTATUS (26) This includes the pin. DCLK (27) This includes the pin. nCEO JTAG Boundary-Scan Testing in Cyclone V Devices Altera Corporation Send Feedback...
Page 275: Power Management In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 276: Hot-Socketing Feature
GND that causes power supply failures. During hot socketing, Cyclone V devices are immune to latch up that can occur when a device is hot- socketed into an active system.
Page 277 The POR circuitry monitors the voltage level of the power supplies and keeps the I/O pins tri-stated until the device is in user mode. The weak pull-up resistor (R) in the Cyclone V input/output element (IOE) is enabled during configuration download to keep the I/O pins from floating.
Page 278: Power-Up Sequence
Cyclone V device, and before configuration starts. These transients have a finite duration bounded by the time at which the device enters configuration mode. For Cyclone V SX, SE and ST devices, you may observe the current transient in the following table after powering up the device, and before all the power supplies reach the recommended operating range.
Page 279: Power-On Reset Circuitry
Provides more information about the PowerPlay EPE support for Cyclone V devices. Power-On Reset Circuitry The POR circuitry keeps the Cyclone V device in the reset state until the power supply outputs are within the recommended operating range. A POR event occurs when you power up the Cyclone V device until the power supplies reach the recommended operating range within the maximum power supply ramp time, t .
Page 280 RAMP The Cyclone V POR circuitry uses an individual detecting circuitry to monitor each of the configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is released after the last ramp-up power reaches the POR trip level during power up.
Page 281: Power Supplies Monitored And Not Monitored By The Por Circuitry
Provides more information about the POR delay specification and t RAMP Power Supplies Monitored and Not Monitored by the POR Circuitry Table 10-2: Power Supplies Monitored and Not Monitored by the Cyclone V POR Circuitry Power Supplies Monitored Power Supplies Not Monitored...
Page 282: Document Revision History
10-8 Document Revision History 2014.01.10 Date Version Changes December 2012 2012.12.28 Added the Power-Up Sequence section. Reorganized content and updated template. June 2012 Restructured the chapter. October 2011 Initial release. Power Management in Cyclone V Devices Altera Corporation Send Feedback...
Page 283 Cyclone V Device Handbook Volume 2: Transceivers CV-5V3 101 Innovation Drive Subscribe 2013.10.17 San Jose, CA 95134 Send Feedback www.altera.com...
Page 284 TOC-2 Cyclone V Device Handbook Volume 2: Transceivers Contents Transceiver Architecture in Cyclone V Devices..........1-1 Architecture Overview..........................1-2 Transceiver Banks..........................1-3 6.144 Gbps CPRI Support Capability in GT Devices..............1-8 Transceiver Channel Architecture....................1-8 PMA Architecture............................1-9 Transmitter PMA Datapath......................1-10 Receiver PMA Datapath........................1-15 Transmitter PLL..........................1-20 Clock Divider..........................1-24...
Page 285 TOC-3 Cyclone V Device Handbook Volume 2: Transceivers PHY IP Embedded Reset Controller......................3-1 Embedded Reset Controller Signals....................3-1 Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Power-Up.............................3-3 Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Operation.............................3-4...
Page 286 Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode..4-29 Channel PLL Feedback for Deterministic Relationship............4-29 CPRI and OBSAI..........................4-30 6.144-Gbps Support Capability in Cyclone V GT Devices............4-31 CPRI Enhancements........................4-32 Document Revision History........................4-34 Transceiver Custom Configurations in Cyclone V Devices.......5-1 Standard PCS Configuration........................5-1...
Page 287 TOC-5 Cyclone V Device Handbook Volume 2: Transceivers Transceiver Channel Reconfiguration......................7-5 Transceiver Interface Reconfiguration ....................7-5 Reduced .mif Reconfiguration ........................7-6 Unsupported Reconfiguration Modes......................7-6 Document Revision History........................7-7 Altera Corporation...
Page 288: Transceiver Architecture In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 289: Architecture Overview
Architecture Overview Figure 1-1: Basic Layout of Transceivers in a Cyclone V Device This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here. I/O, LVDS, and Memory Interface...
Page 290: Transceiver Banks
Every transceiver bank is comprised of three channels (ch 0, ch 1, and ch 2, or ch 3, ch 4 , and ch 5). The Cyclone V device family has a total of four transceiver banks (for the largest density family) namely, GXB_L0, GXB_L1, GXB_L2 and GXB_L3.
Page 291 Bank Names Notes: 1. 4-channel device transceiver channels are located on bank L0, and Ch 5 of bank L1. 2. 6-channel device transceiver channels are located on banks L0 and L1. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 292 Ch 4 Ch 3 Ch 2 PCIe Hard IP GXB_L0 Ch 1 Ch 0 Transceiver Bank Names Note: 1. 9-channel device transceiver channels are located on banks L0, L1, and L2. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 293 Ch 3 Ch 2 PCIe Hard IP GXB_L0 Ch 1 Ch 0 Transceiver Bank Names Note: 1. 12-channel device transceiver channels are located on banks L0, L1, L2, and L3. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 294 Ch 1, Ch 2 GXB_L2 Cyclone V GX transceiver channels are comprised of a transmitter and receiver that can operate individually and simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing. Impacted only if the device has PCIe HIP block located next to this bank.
Page 295: 6.144 Gbps Cpri Support Capability In Gt Devices
6.144 Gbps CPRI Support Capability in GT Devices You can configure Cyclone V GT devices to support 6.144 Gbps for CPRI protocol only. The Cyclone V GT device supports up to three full duplex channels that are compliant to the 6.144 Gbps CPRI protocol for every two transceiver banks.
Page 296: Pma Architecture
PCS. The central clock divider can additionally feed the clock lines used to bond channels compared to the local clock divider. Figure 1-8: PMA Block Diagram of a Transceiver Channel in Cyclone V Devices Transmitter PMA...
Page 297: Transmitter Pma Datapath
If the polarity inversion is asserted midway through a serializer word, the word will be corrupted. Bit Reversal You can reverse the transmission bit order to achieve MSB-to-LSB ordering using the bit reversal feature at the transmitter. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 298 (three-transceiver channels). Note: A maximum of one reconfiguration controller is allowed per transceiver bank. Figure 1-9: Transmitter Buffer Block Diagram in Cyclone V Devices Transmitter Output Tri-State...
Page 299 Reduce Power Programmable Controls the impedance of V . A higher impedance setting Current reduces current consumption from the on-chip biasing Strength circuitry. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 300 PCIe Base Specification 2.0 for Gen1 and Gen2 signaling rates Receiver Detect Supports the receiver detection function as required by the PCIe Base Specification 2.0 for Gen1 and Gen2 signaling rates Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 301 At the receiver end, the termination and biasing circuitry restores the common-mode voltage level that is required by the receiver. Figure 1-11: AC-Coupled Link with a Cyclone V Transmitter The PCIe spec requires that you enable transmitter OCT for receiver detect operation.
Page 302: Receiver Pma Datapath
• PCIe Electrical Idle—The transmitter output buffers support transmission of PCIe electrical idle (or individual transmitter tri-state). Related Information Altera Transceiver PHY IP Core User Guide Receiver PMA Datapath There are three blocks in the receiver PMA datapath—the receiver buffer, channel PLL configured for clock data recovery (CDR) operation, and deserializer.
Page 303 Reduce Power Programmable Controls the impedance of V . A higher impedance setting Current reduces current consumption from the on-chip biasing circuitry. Strength Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 304 You can AC-couple the receiver to a transmitter. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter common-mode voltage. At the receiver end, the termination and biasing circuitry restores the common-mode voltage level that is required by the receiver. Figure 1-13: AC-Coupled Link with a Cyclone V Receiver AC-Coupling Capacitor...
Page 305 CV-53001 1-18 Programmable CTLE and DC Gain 2013.05.06 Figure 1-14: Receiver Buffer Block Diagram in Cyclone V Devices High-speed Differential CTLE – Receiver and DC Gain To CDR PLL Circuitry Channel Input Pins Signal Detect Circuitry Modifying programmable values within receiver input buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired.
Page 306 Use the clock slip feature for applications that require deterministic latency. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 307: Transmitter Pll
PCS. Transmitter PLL In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR) PLL.
Page 308 Notes: 1. Applicable in a PCIe configuration and custom mode configuration, for example SATA/SAS. 2. Applicable when configured as a CDR PLL. 3. Applicable when configured as a CMU PLL. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 309 • In PCIe configurations only—the signal detect circuitry detects the signal level at the receiver input below the threshold voltage specified in the PCI Express Base Specification 2.0 Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 310 LTD mode, direct the CDR PLL to LTR mode. Related Information Transceiver Reset Control and Power Down in Cyclone V Devices Channel PLL as a CMU PLL When you use the channel PLL as the CMU PLL, you can configure the transceiver channel only as a transmitter.
Page 311: Clock Divider
Clock Networks and PLLs in Cyclone V Devices Clock Divider Each Cyclone V transmitter channel has a clock divider. There are two types of clock dividers, depending on the channel location in a transceiver bank: • Local clock divider—channels 0, 2, 3, and 5 provide serial and parallel clocks to the PMA •...
Page 312: Calibration Block
It is also used for duty cycle calibration of the clock line at serial data rates ≥ 4.9152 Gbps. There is only one calibration block available for the Cyclone V transceiver PMA. It is located on the top left of the device (same side as the transceiver channels).
Page 313 CV-53001 1-26 Calibration Block 2013.05.06 Figure 1-20: Calibration Block Location and Connections in Cyclone V Devices Transceivers are on the left side of the device only. 2 kΩ ±1% Calibration RREF Block GXB_L3 GXB_L2 GXB_L1 GXB_L0 Note: 1. GXB_L1, GXB_L2, and GXB_L3 banks are only available in some device variants.
Page 314: Pcs Architecture
CV-53001 1-27 PCS Architecture 2013.05.06 PCS Architecture Figure 1-21: PCS Block Diagram of a Transceiver Channel in a Cyclone V Device The serial and parallel clocks are sourced from the clock divider. Transmitter PMA Transmitter PCS Cyclone V FPGA Fabric...
Page 315: Transmitter Pcs Datapath
The transmitter phase compensation FIFO supports two operations: • Phase compensation mode with various clocking modes on the read clock and write clock • Registered mode with only one clock cycle of datapath latency Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 316 20 bits, the byte serializer sends out the least significant word tx_parallel_data[9:0] of the parallel data from the FPGA fabric, followed by tx_parallel_data[19:10]. Table 1-12: Input and Output Data Width of the Byte Serializer in Single-Width Mode for Cyclone V Devices Mode...
Page 317 32 bits, the byte serializer forwards tx_parallel_data[15:0] first, followed by tx_parallel_data[31:16]. Table 1-13: Input and Output Data Width of the Byte Serializer in Double-Width Mode for Cyclone V Devices Mode Input Data Width to...
Page 318 The 8B/10B block provides the tx_datak signal to indicate whether the 8-bit data at the tx_parallel_data signal should be encoded as a control word (Kx.y) or a data word (Dx.y). When Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 319 Because of some pipelining of the transmitter channel PCS, some “don’t cares” (10’hxxx) are sent before the three synchronizing K28.5 code groups. User data follows the third K28.5 code group. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 320 PMA. The maximum number of bits slipped is controlled from the FPGA fabric and is equal to the width of the PMA-PCS minus 1. Transceiver Architecture in Cyclone V Devices Altera Corporation...
Page 321: Receiver Pcs Datapath
Byte Ordering • Searches for a predefined pattern that must be ordered to the LSByte position in the parallel data going to the FPGA fabric when you enable the byte deserializer Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 322 Mode Pattern Length (bits) Manual User-controlled signal starts the alignment Alignment process. Alignment happens once unless the signal is reasserted. Bit-Slip User-controlled signal shifts data one bit at a time. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 323 Depending on the configuration, controlling the rx_enapatternalign register enables the word aligner to look for the predefined word alignment pattern in the received data stream and automatically synchronizes to the new word boundary. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 324 4. When the word aligner synchronized to the new word boundary, the rx_patterndetect and rx_syncstatus signals will assert for one parallel clock cycle. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 325 Note: For every bit slipped in the word aligner, the earliest bit received is lost. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 326 Protocols such as PCIe require the receiver PCS logic to implement a synchronization state machine to provide hysteresis during link synchronization. Each of these protocols defines a specific number of Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 327 3. When clock-slip is complete, the deserialized data coming into the receiver PCS is word-aligned and indicated when the rx_syncstatus signal asserts. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 328 Table 1-25: Bit Reversal Feature Received Bit Order Bit Reversal Option Single-Width Mode (8 or 10 bit) Double-Width Mode (16 or 20 bit) Disabled (default) LSB to MSB LSB to MSB Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 329 When receiving swapped symbols, the word alignment pattern must be byte-reversed accordingly to match the incoming byte-reversed data. Rate Match FIFO The Rate Match FIFO compensates for the small clock frequency differences between the upstream transmitter and the local receiver clocks. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 330 Related Information • Transceiver Custom Configurations in Cyclone V Devices • Transceiver Protocol Configurations in Cyclone V Devices 8B/10B Decoder The receiver channel PCS datapath implements the 8B/10B decoder after the rate match FIFO. In configu- rations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO.
Page 331 If the received 10-bit code group is one of the 12 control code groups (/Kx.y/) specified in the IEEE802.3 specification, the rx_datak signal is driven high. If the received 10-bit code group is a data code group (/Dx.y/), the rx_datak signal is driven low. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 332 In double-width mode, the byte deserializer receives 16-bit wide data from the 8B/10B decoder or 20-bit wide data from the word aligner (if the 8B/10B decoder is disabled) and deserializes it into 32- or 40-bit wide data at half the speed. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 333 20 bits Disabled 10 bits 10 bits The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 334 The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code. The 18-bit pattern consists of two sets of 9-bit patterns, individually represented as in the previous note. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 335 (1) coreclkout (1) rx_coreclk (1) Note: 1. These clocks may have been divided by 2 if you used a byte deserializer. Related Information Transceiver Clocking in Cyclone V Devices. Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback...
Page 336: Channel Bonding
FIFO in each channel can result in higher channel-to-channel skew. Related Information Transceiver Clocking in Cyclone V Devices PLL Sharing In a Quartus II design, you can merge two different protocol configurations to share the same CMU PLL resources.
Page 337 May 2013 2013.05.06 • Added link to the known document issues in the Knowledge Base • Updated the Transceiver Architecture in Cyclone V Devices section. • Updated the Architecture Overview section. • Updated the Automatic Lock Mode section. • Updated the Transmitter Buffer section.
Page 338 Buffer Features and Capabilities and PMA Receiver Buffer. November 2012 2012.11.19 Reorganized content and updated template June 2012 Added in contents of Transceiver Basics for Cyclone V Devices. Updated “Architecture Overview”, “PMA Architecture” and “PCS Architecture” sections. Updated Table 1 11.
Page 339: Transceiver Clocking In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 340: Dedicated Reference Clock Pins
PCLK) Dedicated Reference Clock Pins Cyclone V devices have one dedicated reference clock (refclk) pin for each bank of three transceiver channels. The dedicated reference clock pins drive the channel PLL in channel 1 or 4 directly. This option provides the best quality of input reference clock to the transmitter PLL and CDR.
Page 341 Only one RX differential pair for every three channels can be used as input reference clock at a time. The following figure shows the use of dual-purpose RX/refclk differential pin as input reference clock source and the RX clock network. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 342: Fractional Pll (Fpll)
50 or 200 MHz in integer mode, or 614.4 MHz in fractional mode. Figure 2-4: fPLL Clock Output as Input Reference Clock fPLL Cascade Clock Network Channel PLL Channel PLL fPLL Channel PLL Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 343: Internal Clocking
CV-53002 Internal Clocking 2013.05.06 Internal Clocking This section describes the clocking architecture internal to Cyclone V transceivers. Different physical coding sublayer (PCS) configurations and channel bonding options result in various transceiver clock paths. Note: The Quartus II software automatically performs the internal clock routing based on the transceiver configuration that you select.
Page 344 • Serial clock—high-speed clock for the serializer • Parallel clock—low-speed clock for the serializer and the PCS Cyclone V transceivers support non-bonded and bonded transceiver clocking configurations: • Non-bonded configuration—Only the serial clock from the transmit PLL is routed to the transmitter channel.
Page 345: Transmitter Clock Network
When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 346 In a bonded configuration, bonded channels must be placed contiguously without leaving a gap between the channels, except when the gap channel is a CMU PLL used for the bonded channels. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 347: Transmitter Clocking
This section describes the clock path for non-bonded configurations. The following table describes the clock path for non-bonded configuration with the CMU PLL and fPLL as TX PLL using various clock lines. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 348 Non-bonded channels within the neighboring two banks or within the six channels of TX PLL are driven by clocks from x6 clock line. Channels in other banks outside the 6 channels are driven by the xN clock line. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 349 TX PMA Ch3 TX PCS Ch3 Local Clock Divider Clock Divider CMU PLL Channels 0, 1, 2 Both Parallel and Serial Clocks Data Path Serial Clock Unused Resources Parallel Clock Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 350 This section describes the clock path for bonded configurations. The following table describes the clock path for bonded configurations with the CMU PLL as TX PLL using various clock lines. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 351 Bonded channels within the neighboring two banks or within the six channels of TX PLL are driven by clocks from x6 clock line. Channels in other banks outside the 6 channels are driven by the xN clock line. Transceiver Clocking in Cyclone V Devices Altera Corporation...
Page 352: Receiver Clocking
Byte deserializer Read Divided down version of the write side clock depending on the deserialization factor of 1 or 2, also called the parallel clock (divided) Byte ordering Parallel clock (divided) Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 353 When the rate match FIFO is not enabled, the receiver PCS in every channel uses the parallel recovered clock. When the rate match FIFO is enabled, the receiver PCS in every channel uses both the parallel recovered clock and parallel clock from the clock divider. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 354 Clock Clock Divider Clock Divider) CMU PLL To Transmitter Channel From the x6 or xN Clock Lines Both Parallel and Serial Clocks Data Path Serial Clock Unused Resources Parallel Clock Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 355 1 or 4. Note: For more information about the clocking scheme used in different configurations, refer to the Transceiver Protocol Configurations in Cyclone V Devices and Transceiver Custom Configurations in Cyclone V Devices chapters. Transceiver Clocking in Cyclone V Devices...
Page 356: Fpga Fabric Transceiver Interface Clocking
Clock Lines Parallel Clock Receiver Related Information Transceiver Protocol Configurations in Cyclone V Devices Transceiver Custom Configurations in Cyclone V Devices FPGA Fabric Transceiver Interface Clocking This section describes the clocking options available when the transceiver interfaces with the FPGA fabric.
Page 357 ® • mgmt_clk—Avalon -MM interface clock used for controlling the transceivers, dynamic reconfigu- ration, and calibration • fixed_clk—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 358 For more information about the GCLK, RCLK, and PCLK resources available in each device, refer to the Clock Networks and PLLs in Cyclone V Devices chapter. The mgmt_clk is a free-running clock that is not derived from the transceiver blocks.
Page 359: Transceiver Datapath Interface Clocking
Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices chapters. You can clock the transmitter datapath interface with one of the following options: •...
Page 360 Quartus II-Software Selected Transmitter Datapath Interface Clock 2013.05.06 Related Information • Transceiver Custom Configurations in Cyclone V Devices • Transceiver Protocol Configurations in Cyclone V Devices Quartus II-Software Selected Transmitter Datapath Interface Clock The Quartus II software automatically selects the appropriate clock from the FPGA fabric to clock the transmitter datapath interface.
Page 361 To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface of all identical transmitter channels. The following figure shows six identical channels clocked by a single clock (tx_clkout of channel 4). Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 362 You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins. Transceiver Clocking in Cyclone V Devices Altera Corporation...
Page 363: Receiver Datapath Interface Clock
Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices chapters. You can clock the receiver datapath interface with one of the following options: •...
Page 364 Data and Status Logic Compensation FIFO rx_coreclkin[1] Parallel Clock (Recovered Clock) rx_clkout[0] Channel 0 Channel 0 Receiver Receiver Data Phase Receiver Data Data and Status Logic Compensation FIFO rx_coreclkin[0] Parallel Clock (Recovered Clock) Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 365 Channel 7 rx_coreclkin[6] Channel 6 rx_coreclkin[5] Channel 5 rx_coreclkin[4] Channel [7:0] Receiver Data and Control Logic Channel 4 rx_clkout[4] rx_coreclkin[3] Channel 3 rx_coreclkin[2] Channel 2 rx_coreclkin[1] Channel 1 rx_coreclkin[0] Channel 0 Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 366: Document Revision History
• Added link to the known document issues in the Knowledge Base. November 2012 2012.11.19 • Reorganized content and updated template. • Updated for the Quartus II software version 12.1. June 2012 Minor editorial changes. October 2011 Initial release. Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback...
Page 367: Transceiver Reset Control In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 368 A continuous high on this signal indicates that the rx_ready receiver (RX) channel is out of reset and is ready for data reception. This signal is synchronous to phy_ mgmt_clk. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 369: Resetting The Transceiver With The Phy Ip Embedded Reset Controller During Device Power-Up
2. After the transmitter calibration and reset sequence are complete, the tx_ready status signal is asserted and remains asserted to indicate that the transmitter is ready to transmit data. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 370: Resetting The Transceiver With The Phy Ip Embedded Reset Controller During Device Operation
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did not complete successfully and the link will be down. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 371: User-Coded Reset Controller
• The internal signals of the PHY IP embedded reset controller are configured as ports • You can hold the transceiver channels in reset by asserting the appropriate reset control signals Transceiver Reset Control in Cyclone V Devices Altera Corporation...
Page 372: User-Coded Reset Controller Signals
User-Coded Reset Controller Signals 2013.05.06 Related Information "Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP Core User Guide. For information about the transceiver PHY reset controller. User-Coded Reset Controller Signals Use the signals in the following figure and table with a user-coded reset controller.
Page 373: Resetting The Transmitter With The User-Coded Reset Controller During Device Power-Up
• pll_locked is asserted • tx_cal_busy is deasserted The transmitter is out of reset and ready for operation. Note: During calibration, pll_locked might assert and deassert as the calibration IP runs. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 374: Resetting The Transmitter With The User-Coded Reset Controller During Device Operation
2. After the transmitter PLL locks, the pll_locked status is asserted after t . While the TX PLL pll_lock locks, the pll_locked status signal may toggle. It is asserted after t pll_lock Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 375: Resetting The Receiver With The User-Coded Reset Controller During Device Power-Up Configuration
Ensure rx_analogreset and rx_cal_busy are deasserted before deasserting rx_digitalreset. The receiver is now out of reset and ready for operation. Note: rx_is_lockedtodata might toggle when there is no data at the receiver input. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 376: Resetting The Receiver With The User-Coded Reset Controller During Device Operation
Ensure rx_analogreset is de-asserted. Note: rx_is_lockedtodata might toggle when there is no data at the receiver input. rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 377: Transceiver Reset Control Signals Using Avalon Memory Map Registers
RX CDR PLL is in the lock to reference (LTR) mode if pma_rx_set_lockedtodata is not asserted. The default is low when both registers have the CDR in auto lock mode. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 378: Clock Data Recovery Manual Lock Mode Reset Sequence
Use the following control signals to reset the transceiver when the CDR is in manual lock mode. Table 3-5: Control Settings for the CDR in Manual Lock Mode rx_set_locktoref rx_set_locktodata CDR Lock Mode Automatic Manual-RX CDR LTR Manual-RX CDR LTD Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 379: Resetting The Transceiver In Cdr Manual Lock Mode
Reset is required for transceiver during dynamic reconfiguration except in the PMA Analog Control Reconfiguration mode. In general, follow these guidelines when dynamically reconfiguring the transceiver: 1. Hold the targeted channel and PLL in the reset state before dynamic reconfiguration starts. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 380: Guidelines For Dynamic Reconfiguration If Transmitter Duty Cycle Distortion Calibration Is Required During Device Operation
Receiver Rate Match FIFO — — — — Receiver 8B/10B Decoder — — — — Receiver Byte Deserializer — — — — Receiver Byte Ordering — — — — Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 381: Transceiver Power-Down
For information about the transceiver power supply operating conditions of the left and right side of Cyclone V devices. Document Revision History Date Version Changes • Changed term of User-Controlled Reset Controller to User-Coded Reset Controller. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 382 • Included sequences for resetting transceiver during device operation November 2011 • Added “User-Controlled Reset Controller” section. • Updated Figure 3 1 and Table 3 1. August 2011 Initial release. Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback...
Page 383 Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 384: Transceiver Protocol Configurations In Cyclone V Devices
The Cyclone V PCIe Hard IP operates independently from the core logic, which allows the PCIe link to wake up and complete link training in less than 100 ms while the Cyclone V device completes loading the programming file for the rest of the device.
Page 385: Pipe Transceiver Datapath
PCS–Hard IP Interface Frequency Gen1 - 250 MHz Gen2 - 500 MHz Note: Refer to the Cyclone V Device Datasheet for the mgmt_clk_clk frequency specification when PCIe HIP is used. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 386: Pcie Supported Features
• 16-bit FPGA fabric transceiver interface • Transmitter buffer electrical idle • Receiver detection • 8B/10B encoder disparity control when transmitting compliance pattern • Power state management (Electrical Idle only) • Receiver status encoding Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 387 The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine (LTSSM) enters a polling compliance substate. The polling compliance substate assesses if the transmitter is electrically compliant with the PCIe voltage and timing specifications. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 388 PCIe specification. Receiver Detection The PIPE interface block in Cyclone V transceivers provides an input signal (pipe_txdetectrx_loopback) for the receiver detect operation that is required by the PCIe protocol during the detect substate of the LTSSM.
Page 389: Pcie Supported Configurations And Placement Guidelines
PCIe Hard IP blocks in the device separately. In the following figures, channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 390 Figure 4-6: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement Transceiver Bank PCIe Hard IP CMU PLL PCIe x1 Master Transceiver Bank PCIe Hard IP CMU PLL PCIe x1 Master Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 391 Figure 4-8: 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement Transceiver Bank PCIe Hard IP CMU PLL PCIe x1 Master Transceiver Bank PCIe Hard IP CMU PLL PCIe x1 Master Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 392 For PCIe Gen1 and Gen2, there are restrictions on the achievable x1 and x4 bonding configurations if you intend to use both top and bottom Hard IP blocks in the device. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation...
Page 393: Gigabit Ethernet
Table 4-2: Hard IP Configurations for PCIe Gen1 and Gen2 The following table lists the configurations allowed for each Cyclone V device when you use both PCIe Hard IP blocks on the top and bottom transceiver banks. Support will vary by the number of transceiver channels in a device.
Page 394 The transceivers do not have built-in support for other PCS functions, such as the autonegotiation state machine, collision-detect, and carrier-sense functions. If you require these functions, implement them in the FPGA fabric or in external circuits. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 395: Gigabit Ethernet Transceiver Datapath
FPGA Fabric–Transceiver Interface Clock Receiver Channel PCS Receiver Channel PMA Rate RX Phase 8B/10B Word Match Deserializer Compensation Decoder Aligner FIFO FIFO rx_coreclk[0] Parallel Recovered Clock Low-Speed Parallel Clock Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 396 FIFO from overflowing or underrunning. The rate matcher can insert or delete as many /I2/ ordered sets as necessary to perform the rate match operation. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation...
Page 397 Number of errors received to lose synchronization Number of continuous good code groups received to reduce the error count by 1 (12) Two data code groups represent the Config_Reg value. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 398: Xaui
= 3 Related Information Refer to the "Custom PHY IP Core" and "Native PHY IP Core" chapters in the Altera Transceiver PHY IP Core User Guide XAUI In a XAUI configuration, the transceiver channel data path is configured using soft PCS. It provides the transceiver channel datapath description, clocking, and channel placement guidelines.
Page 399: Transceiver Datapath In A Xaui Configuration
10 Gbps Related Information Refer to the "XAUI PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide. Transceiver Datapath in a XAUI Configuration The XAUI PCS is implemented in soft logic inside the FPGA core when using the XAUI PHY IP core. You must ensure that your channel placement is compatible with the soft PCS implementation.
Page 400 Deskew FIFO Enabled Rate Match FIFO Enabled Byte SERDES Enabled Byte Ordering Disabled FPGA Fabric-to-Transceiver 16-Bit Interface Width FPGA Fabric-to-Transceiver Interface Frequency 156.25 MHz Note: 1. Implemented in soft logic. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 401: Xaui Supported Features
(DDR) of the 156.25 MHz interface clock. Cyclone V transceivers and soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in IEEE 802.3-2008 specification. Instead, they allow the transferring of 16-bit data and 2-bit control code on each of the four XAUI lanes, only at the positive edge (SDR) of the 156.25...
Page 402 Transmitter and Receiver State Machines In a XAUI configuration, the Cyclone V soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification. In addition to encoding the XGMII data to PCS code groups, in conformance with the 10GBASE-X PCS, the transmitter state diagram performs functions such as converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R|| ordered sets.
Page 403 • The lane aligner indicates a successful lane deskew. The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column for clock rate compensation. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 404: Transceiver Clocking And Channel Placement Guidelines In Xaui Configuration
This method uses xgmii_rx_clk to compensate for the phase difference on the TX side. Without this method, the tx_digitalreset signal may experience intermittent failure. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 405 In the soft PCS implementation of the XAUI configuration, all four channels must be placed continuously. The channels may all be placed in one bank or they may span two banks. Only the placements shown in the following figure are allowed. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 406: Serial Digital Interface
Related Information To implement the QSF assignment workaround using the Assignment Editor, refer to the "XAUI PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide. Serial Digital Interface The Society of Motion Picture and Television Engineers (SMPTE) defines various Serial Digital Interface (SDI) standards for transmission of uncompressed video.
Page 407: Configurations Supported In Sdi Mode
Rate Match FIFO Disabled Disabled Byte SERDES Enabled Disabled Enabled Byte Ordering Disabled Disabled Disabled FPGA Fabric-Transceiver 20-bit Interface Width 10-bit 20-bit FPGA Fabric-Transceiver 148.5/148.35 148.5/148.35 74.25/74.175 Interface Frequency (MHz) Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 408: Serial Digital Interface Transceiver Datapath
FPGA logic array. Receiver Word Alignment and Framing In SDI systems, the word aligner in the receiver datapath is not useful because the word alignment and framing happen after descrambling. Altera recommends that you drive the rx_bitslip of the PHY ™ MegaWizard signal low to avoid having the word aligner insert bits in the received data stream.
Page 409: Sata And Sas Protocols
These serial storage protocols offer several advantages over older parallel storage protocol (ATA and SCSI) interfaces: • Faster data transfer • Hot swapping (when supported by the operating system) • Thinner cables for more efficient air cooling • Increased operation reliability Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 410 Configuration Option Configuration Option Configuration Option for SATA/SAS for SATA/SAS for SATA/SAS for SATA/SAS 1.5 Gbps Data Rate 3.0 Gbps Data Rate 1.5 Gbps Data Rate 3.0 Gbps Data Rate Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 411: Deterministic Latency Protocols-Cpri And Obsai
CPRI protocol, which places stringent requirements on the amount of latency variation, you must choose a reference clock of 122.88 MHz to allow the usage of a feedback path from the channel PLL. This feedback path reduces the variations in latency. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 412: Cpri And Obsai
The baseband module processes the encoded signal and brings it back to the baseband before transmitting it to the terrestrial network using the transport module. A control module maintains the coordination between these three functions. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 413: 6.144-Gbps Support Capability In Cyclone V Gt Devices
6.144-Gbps Support Capability in Cyclone V GT Devices Cyclone V GT devices support a 6.144 Gbps data rate for the CPRI protocol only. For CPRI 6.144-Gbps transmit jitter compliance, Altera recommends you use only up to three full-duplex channels for every two transceiver banks.
Page 414: Cpri Enhancements
The reference clock frequency for the 6.144 Gbps CPRI channel must be ≥ 307.2 MHz. The maximum number of transceiver channels in a Cyclone V GT device that can achieve 6.144-Gbps CPRI compliance is based on: • Transceiver performance in meeting the TX jitter specification for 6.144-Gbps CPRI.
Page 415 Related Information Refer to the "Deterministic Latency PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide (14) Enhanced deterministic latency feature in Cyclone V devices. Transceiver Protocol Configurations in Cyclone V Devices...
Page 416: Document Revision History
• Added the "6-Gbps Support Capability in Cyclone V GT Devices" section. November 2012 2012.11.19 • Reorganized content and updated template. • Added the "XAUI" section. • Added the "PCI Express" section. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 417 • Added the “Serial Digital Interface” section. • Added the “Serial Data Converter (SDC) JESD204” section. • Added the “SATA and SAS Protocols” section. October 2011 Initial release. Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 418: Standard Pcs Configuration
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 419: Custom Configuration Channel Options
The following table shows the maximum supported data rate for the fastest speed grade in Standard PCS (transceiver speed grade 6) for Cyclone V GX and SX devices, and (transceiver speed grade 5) for Cyclone V GT and ST devices.
Page 420 Figure 5-3: Configuration Options for Custom Single-Width Mode (8-bit PMA PCS Interface Width) Manual Alignment Word Aligner (Pattern Length) or Bit-Slip 8B/10B Encoder/Decoder Disabled Rate Match FIFO Disabled Byte SERDES Disabled Enabled FPGA Fabric–Transceiver 8-Bit 16-Bit Interface Width Data Rate (Gbps) Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 421 Word Aligner (Pattern Length) or Bit-Slip 8B/10B Encoder/Decoder Disabled Rate Match FIFO Disabled Byte SERDES Disabled Enabled FPGA Fabric–Transceiver 16-Bit 32-Bit Interface Width Data Rate (Gbps) GX/SX= 3.125 2.62144 GT/ST= 5 Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 422: Rate Match Fifo In Custom Configuration
Full Condition Deletes the data byte that causes the FIFO to go full. Empty Condition Inserts a /K30.7/ (9'h1FE) after the data byte that caused the FIFO to go empty. Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 423: Standard Pcs In Low Latency Configuration
To provide a low latency datapath, the PCS includes only the phase compensation FIFO in phase compensation mode, and optionally, the byte serializer and byte deserializer blocks, as shown in the following figure. The transceiver channel interfaces with the FPGA fabric through the PCS. Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 424: Low Latency Custom Configuration Channel Options
• The blocks shown as “Disabled” are not used but incur latency. • The blocks shown as “Bypassed” are not used and do not incur any latency. • The transmitter bit-slip is disabled. Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 425 8B/10B Encoder/Decoder Disabled Rate Match FIFO Bypassed Byte SERDES Bypassed Enabled Byte Ordering Bypassed Bypassed FPGA Fabric–Transceiver 10-Bit 20-Bit Interface Width GX/SX= 3.125 Data Rate (Gbps) 1.875 GT/ST= 3.75 Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 426 Rate Match FIFO Bypassed Byte SERDES Bypassed Enabled Byte Ordering Bypassed Bypassed FPGA Fabric–Transceiver 20-Bit 40-Bit Interface Width GX/SX= 3.125 GX/SX= 3.125 Data Rate (Gbps) GT/ST= 3.2768 GT/ST= 5 Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 427: Document Revision History
Added link to the known document issues in the Knowledge Base. November 2012 2012.11.19 Reorganized content and updated template. June 2012 Updated for the Quartus II software version 12.0 release. October 2011 Initial release. Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback...
Page 428: Transceiver Loopback Support
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 429: Forward Parallel Loopback
Transmitter PCS FPGA Fabric Forward Parallel Loopback Path PRBS Gen Receiver PMA Receiver PCS PRBS Checker Note: Usage details for the feature are described in the Altera Transceiver PHY IP Core User Guide. Transceiver Loopback Support Altera Corporation Send Feedback...
Page 430: Pipe Reverse Parallel Loopback
You can enable reverse serial loopback through the reconfiguration controller. Note: For further details, refer to the Altera Transceiver PHY IP Core User Guide. In reverse serial loopback, the data is received through the rx_serial_data port, re-timed through the receiver CDR, and sent to the tx_serial_data port. The received data is also available to the FPGA logic.
Page 431: Reverse Serial Pre-Cdr Loopback
You can enable reverse serial pre-CDR loopback through the reconfiguration controller. Note: For further details, refer to the Altera Transceiver PHY IP Core User Guide. In reverse serial pre-CDR loopback, the data received through the rx_serial_data port is looped back to the tx_serial_data port before the receiver CDR.
Page 432: Document Revision History
Datapath Note: Grayed-out blocks are not active when the reverse serial pre-CDR loopback is enabled. Related Information Altera Transceiver PHY IP Core User Guide Document Revision History The table below lists the revision history for this chapter. Table 6-1: Document Revision History...
Page 433: Dynamic Reconfiguration In Cyclone V Devices
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 434: Offset Cancellation
(mgmt_rst_reset) until the clock is stable. Transmitter Duty Cycle Distortion Calibration The duty cycle calibration function tunes the transmitter to minimize duty cycle distortion. Dynamic Reconfiguration in Cyclone V Devices Altera Corporation Send Feedback...
Page 435: Pma Analog Controls Reconfiguration
AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices • Altera Transceiver PHY IP Core User Guide PMA Analog Controls Reconfiguration You can dynamically reconfigure the analog controls setting after offset cancellation is complete and the reset sequence is performed.
Page 436: Dynamic Reconfiguration Of Loopback Modes
Serial loopback can be implemented with the transceiver PHY IP directly using the Avalon interface or a control port. Related Information • Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide • Transceiver Loopback Support in Cyclone V Devices Transceiver PLL Reconfiguration You can use the PLL reconfiguration registers to switch the reference clock input to the TX PLL or the clock data recovery (CDR) circuitry.
Page 437: Transceiver Channel Reconfiguration
Transceiver Reconfiguration Controller. PLL reconfiguration affects all channels that are currently using that PLL for transmission. Channel reconfiguration from either a transmitter-only configuration to a receiver-only configuration or vice versa is not allowed. Dynamic Reconfiguration in Cyclone V Devices Altera Corporation Send Feedback...
Page 438: Reduced .Mif Reconfiguration
CMU PLL reconfiguration mode Related Information Channel and PLL Reconfiguration” section in the Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide For information about transceiver channel and PLL reconfiguration. Reduced .mif Reconfiguration Reduce reconfiguration time by reconfiguring only the affected blocks in the transceiver channels.
Page 439: Document Revision History
November 2012 2012.11.19 • Rewritten and reorganized content, and updated template • Added TX DCD • Added Transceiver PLL Reconfigu- ration • Transceiver Channel Reconfigura- tion • Listed unsupported features Dynamic Reconfiguration in Cyclone V Devices Altera Corporation Send Feedback...
Page 440 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual cv_5v4 101 Innovation Drive Subscribe 2013.12.30 San Jose, CA 95134 Send Feedback www.altera.com...
Page 441 TOC-2 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Contents Introduction to Cyclone V Hard Processor System (HPS)........1-1 Features of the HPS............................1-2 HPS Block Diagram and System Integration...................1-3 MPU Subsystem..........................1-4 Interconnect............................1-4 Memory Controllers........................1-4 Support Peripherals.........................1-7 Interface Peripherals........................1-8 On-Chip Memory..........................1-11...
Page 442 TOC-3 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual HPS External Reset Sources......................3-3 Reset Controller..........................3-4 Module Reset Signals........................3-5 Slave Interface and Status Register....................3-9 Functional Description of the Reset Manager..................3-9 Reset Sequencing..........................3-10 Reset Pins............................3-12 Reset Effects............................3-13 Altering Warm Reset System Response..................3-13 Reset Handshaking........................3-14...
Page 443 TOC-4 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual AXI Bridges Block Diagram and System Integration................5-2 Functional Description of the AXI Bridges....................5-3 The Global Programmers View.....................5-3 FPGA-to-HPS Bridge........................5-3 HPS-to-FPGA Bridge........................5-7 Lightweight HPS-to-FPGA Bridge....................5-10 Clocks and Resets...........................5-13 Data Width Sizing..........................5-14...
Page 444 TOC-5 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual HPS Debug APB Interface......................7-10 CoreSight Debug and Trace Programming Model................7-10 ROM Table............................7-10 STM Channels..........................7-11 FPGA Interface..........................7-12 CTI Trigger Connections to Outside the Debug System............7-14 Configuring Embedded Cross-Trigger Connections..............7-15 Debug Clocks..........................7-16...
Page 445 TOC-6 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Protocol Details..........................8-17 SDRAM Controller Subsystem Programming Model................8-23 HPS Memory Interface Architecture......................8-23 HPS Memory Interface Configuration....................8-24 HPS Memory Interface Simulation......................8-24 Generating a Preloader Image for HPS with EMIF................8-25 Creating a Qsys Project in Preparation for Generating a Preloader Image......8-25...
Page 446 TOC-7 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Resets...............................10-5 Indexed Addressing........................10-5 Command Mapping........................10-6 Data DMA.............................10-12 Command DMA..........................10-16 ECC..............................10-24 Interface Signals...........................10-27 NAND Flash Controller Programming Model...................10-28 Basic Flash Programming......................10-28 Flash-Related Special Function Operations................10-32 NAND Flash Controller Address Map and Register Definitions.............10-39 Document Revision History........................10-40...
Page 447 TOC-8 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual SD/MMC Controller Address Map and Register Definitions............11-72 Document Revision History........................11-72 Quad SPI Flash Controller................12-1 Features of the Quad SPI Flash Controller.....................12-1 Quad SPI Flash Controller Block Diagram and System Integration..........12-2 Functional Description of the Quad SPI Flash Controller..............12-3...
Page 448 TOC-9 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual FPGA Manager Building Blocks....................13-3 FPGA Configuration........................13-4 Clock..............................13-7 Reset..............................13-8 FPGA Manager Address Map and Register Definitions..............13-8 Document Revision History........................13-8 System Manager....................14-1 Features of the System Manager......................14-1 System Manager Block Diagram and System Integration..............14-2 Functional Description of the System Manager..................14-3...
Page 449 TOC-10 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Functional Description of the DMA Controller..................16-3 Operating States..........................16-4 Error Checking and Correction....................16-7 Initializing the DMAC........................16-7 Using the Slave Interfaces......................16-9 Peripheral Request Interface......................16-10 Using Events and Interrupts......................16-14 Aborts............................16-15 Security Usage..........................16-18...
Page 450 TOC-11 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual IEEE 1588-2002 Timestamps.....................17-11 IEEE 1588-2008 Advanced Timestamps..................17-17 IEEE 802.3az Energy Efficient Ethernet...................17-19 Checksum Offload........................17-19 Frame Filtering..........................17-20 Clocks and Resets.........................17-22 Resets.............................17-22 Interrupts............................17-23 Ethernet MAC Programming Model....................17-23 DMA Controller...........................17-23 Descriptor Overview........................17-36...
Page 451 TOC-12 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual SPI Controller....................19-1 Features of the SPI Controller........................19-1 SPI Block Diagram and System Integration...................19-1 SPI Block Diagram.........................19-2 Functional Description of the SPI Controller..................19-2 Protocol Details and Standards Compliance................19-2 SPI Controller Overview.......................19-3...
Page 452 TOC-13 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Interface Pins..........................20-12 C Controller Programming Model.....................20-13 Slave Mode Operation.........................20-13 Master Mode Operation......................20-16 Disabling the I2C Controller......................20-17 DMA Controller Operation.......................20-17 C Controller Address Map and Register Definitions..............20-21 Document Revision History........................20-21 UART Controller....................21-1...
Page 453 TOC-14 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Clocks..............................23-2 Resets...............................23-3 Interrupts............................23-3 Timer Programming Model........................23-3 Initialization............................23-3 Enabling the Timer........................23-4 Disabling the Timer........................23-4 Loading the Timer Countdown Value..................23-4 Servicing Interrupts........................23-4 Timer Address Map and Register Definitions..................23-5 Document Revision History........................23-5 Watchdog Timer....................24-1...
Page 454 TOC-15 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual Automatic Retransmission......................25-8 Test Mode............................25-8 L4 Slave Interface...........................25-9 Clocks..............................25-9 Software Reset..........................25-10 Hardware Reset..........................25-10 Interrupts............................25-10 CAN Controller Programming Model....................25-11 Software Initialization.........................25-11 CAN Message Transfer.......................25-12 Message Object Reconfiguration for Frame Reception............25-12 Message Object Reconfiguration for Frame Transmission............25-13...
Page 455 TOC-16 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual HPS Component Interfaces................28-1 Memory-Mapped Interfaces........................28-2 FPGA-to-HPS Bridge........................28-2 HPStoFPGA and Lightweight HPS-to-FPGA Bridges.............28-3 FPGA-to-HPS SDRAM Interface....................28-3 Clocks................................28-5 Alternative Clock Inputs to HPS PLLs..................28-5 User Clocks.............................28-5 AXI Bridge FPGA Interface Clocks.....................28-5 SDRAM Clocks..........................28-5...
Page 456 TOC-17 Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual FPGA-to-HPS System Trace Macrocell (STM) Hardware Event Interface........29-7 HPS-to-FPGA Cross-Trigger Interface....................29-8 HPS-to-FPGA Trace Port Interface......................29-8 FPGA-to-HPS DMA Handshake Interface....................29-8 Simulation Flows............................29-10 Specifying HPS Simulation Model in Qsys................29-10 Generating HPS Simulation Model in Qsys................29-13...
Page 457 Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 458: Introduction To Cyclone V Hard Processor System (Hps)
For information about the FPGA portion of the device, refer to Cyclone V Device Handbook. • Booting and Configuration For more information, refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook. Features of the HPS The following list contains the main modules of the HPS: •...
Page 459: Hps Block Diagram And System Integration
32-Bit Flash L4, 32-Bit Bus Watchdog Timer UART GPIO Clock Reset Scan System Timer Manager Manager Manager Manager The HPS incorporates third-party intellectual property (IP) from several vendors. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 460: Mpu Subsystem
Each L4 bus operates on a separate clock source. Related Information Interconnect on page 4-1 Memory Controllers SDRAM Controller Subsystem The SDRAM controller subsystem is mastered by HPS masters and FPGA fabric masters. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 461 SDRAM Controller Subsystem on page 8-1 DDR PHY The DDR PHY interfaces the single port memory controller to the HPS memory I/O. Related Information SDRAM Controller Subsystem on page 8-1 Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 462 • Up to 64 KB programmable block size Note: For an inclusive list of the programmable card types versions supported, refer to the SD/MMC Controller chapter. Related Information SD/MMC Controller on page 11-1 Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 463: Support Peripherals
• Free-running timer mode • Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock frequency) • Interrupt generation Related Information Timer Introduction on page 23-1 Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 464: Interface Peripherals
The two EMACs are based on the Synopsys DesignWare 3504-0 Universal 10/100/1000 Ethernet MAC and offer the following features: • Supports 10, 100, and 1000 Mbps standard • Supports RGMII external PHY interface • Integrated DMA controller Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 465 • Support master and slave operating mode • Direct access for host processor • DMA controller may be used for large transfers Related Information C Controller on page 20-1 Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 466 • Programmable data frame size from 4 to 16 bits • Supports full and half duplex • Direct access for host processor • DMA controller may be used for large transfers Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 467: On-Chip Memory
The FPGA-to-HPS, HPS-to-FPGA, FPGA-to-SDRAM, and lightweight HPS-to-FPGA interfaces are little- endian. If a processor is set to BE8 mode, software must convert endianness for accesses to peripherals and DMA linked lists in memory. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 468: Hps-Fpga Interfaces
For information about the coherent memory interface, refer to the Cortex A9 MPU System chapter in volume 3 of the Cyclone V Device Handbook. • HPS-to-FPGA bridge a high-performance AXI interface with a configurable data width of 32, 64, and 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric.
Page 469 The following table shows the base address and size of each region that is common to the L3 and MPU address spaces. Table 1-2: Common Address Space Regions Identifier Region Name Base Address Size FPGASLAVES FPGA slaves 0xC0000000 960 MB Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 470 0x100000. The L3 interconnect Global Programmers View (GPV) remap control register determines if the boot region is mapped to the on-chip RAM or the boot ROM. For information about the This space is part of the "PERIPH" space. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 471 MPU address space. For more information about the ACP ID mapper, ® refer to the Cortex A9 MPU System chapter in volume 3 of the Cyclone V Device Handbook. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 472: Hps Peripheral Region Address Map
HPS-to-FPGA AXI bridge 0xFF500000 1 MB FPGA2HPSREGS FPGA-to-HPS AXI bridge 0xFF600000 1 MB EMAC0 EMAC0 0xFF700000 8 KB EMAC1 EMAC1 0xFF702000 8 KB SDMMC SD/MMC 0xFF704000 4 KB Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 473 4 KB SPTIMER0 SP Timer0 0xFFC08000 4 KB SPTIMER1 SP Timer1 0xFFC09000 4 KB SDRREGS SDRAM controller 0xFFC20000 128 KB subsystem registers OSC1TIMER0 OSC1 Timer0 0xFFD00000 4 KB Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 474: Document Revision History
Version Changes December 2013 2013.12.30 Maintenance release November 2012 Minor updates. June 2012 Updated address spaces section. May 2012 Added peripheral region address map. January 2012 Initial release. Introduction to Cyclone V Hard Processor System (HPS) Altera Corporation Send Feedback...
Page 475: Clock Manager
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 476: Clock Manager Block Diagram And System Integration
Refer to Hardware-Managed and Software-Managed Clocks section of this chapter. Clock Manager Block Diagram and System Integration The following figure shows the major components of the clock manager and its integration in the HPS. Clock Manager Altera Corporation Send Feedback...
Page 477: Functional Description Of The Clock Manager
• Divider range is 1 to 64 • Six post-scale counters (C0-C5) with a range of 1 to 512 • PLL can be enabled to bypass all outputs to the osc1_clk clock for glitch-free transitions Clock Manager Altera Corporation Send Feedback...
Page 478 Cyclone V Device Datasheet Minimum and maximum VCO frequencies for the main, peripheral, and SDRAM PLLs vary by device speed grade. For specific details, refer the Cyclone V Device Datasheet. Dividers Dividers subdivide the C0-C5 clocks produced by the PLL to lower frequencies. The main PLL C0-C2 clocks have an additional internal post-scale counter.
Page 479: Hardware-Managed And Software-Managed Clocks
The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are derived from the main PLL. The main PLL is always sourced from the EOSC1 pin of the device. Clock Manager Altera Corporation Send Feedback...
Page 480 Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks. Clock Manager Altera Corporation Send Feedback...
Page 481 For these registers, hardware detects that the write has occurred and performs the correct sequence to ensure that a glitch-free transition to the new clock value occurs. These clocks can pause during the transition. Clock Manager Altera Corporation Send Feedback...
Page 482 Clock for the trace timestamp dbg_timer_clk generator Clock for Debug Access Port dbg_at_clk/2 or dbg_at_clk/ dbg_clk (DAP) and debug peripheral bus Main PLL C3 Quad SPI flash internal logic clock main_qspi_clk Main PLL C4 Clock Manager Altera Corporation Send Feedback...
Page 483 Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example, cycle 15 of the divide-by-16 divider for the main C2 output and cycle 3 of the divide-by-4 divider for the C1 output. Clock Manager Altera Corporation Send Feedback...
Page 484 Clock gate blocks in the diagram indicate clocks which may be gated off under software control. Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks. Clock Manager Altera Corporation Send Feedback...
Page 485 1, 2, 4, 8, or 16 Divide by can0_clk Clock Gate 1, 2, 4, 8, or 16 Divide by can1_clk Clock Gate 1, 2, 4, 8, or 16 24-Bit Clock Gate gpio_db_clk Divider Clock Gate h2f_user1_clock Clock Manager Altera Corporation Send Feedback...
Page 486 The SDRAM clock group consists of a PLL and clock gating. The clocks in the SDRAM clock group are derived from the SDRAM PLL. The SDRAM PLL can be programmed to be sourced from the EOSC1 pin, the EOSC2 pin, or the f2h_sdram_ref_clk clock provided by the FPGA fabric. Clock Manager Altera Corporation Send Feedback...
Page 487 Unused Unused h2f_user2_base_clk h2f_user2_clock Clock Gate The SDRAM PLL output clocks can be phase shifted in real time in increments of 1/8 the VCO frequency. Maximum number of phase shift increments is 4096. Clock Manager Altera Corporation Send Feedback...
Page 488: Flash Controller Clocks
FPGA fabric. Figure 2-6: Flash Peripheral Clock Divide and Gating f2h_periph_ref_clk main_nand_sdmmc_base_clk Clock Gate sdmmc_clk periph_nand_sdmmc_base_clk nand_x_clk f2h_periph_ref_clk Divide by 4 nand_clk Clock Gate main_nand_sdmmc_base_clk Clock Gate periph_nand_sdmmc_base_clk f2h_periph_ref_clk qspi_clk Clock Gate main_qspi_base_clk periph_qspi_base_clk Clock Manager Altera Corporation Send Feedback...
Page 489: Resets
The reset manager can request that the clock manager go into safe mode as part of the reset manager’s warm reset sequence. Before asserting safe mode to the clock manager, the reset manager ensures that the reset signal is asserted on all modules that receive warm reset. Clock Manager Altera Corporation Send Feedback...
Page 490: Safe Mode
Related Information Reset Manager on page 3-1 For more information, refer to “Reset Sequencing” in the Reset Manager chapter in the Cyclone V Device Handbook, Volume 3. Safe Mode Safe mode is enabled in the HPS by the assertion of a safe mode request from the reset manager or by a cold reset.
Page 491 Clock for the USB masters and usb_mp_clk slaves Clock for the NAND master nand_x_clk Clock for the FPGA manager cfg_clk configuration data slave Clock for the L3 slave peripheral l3_sp_clk switch Clock for the L4 SPIS bus master l3_main_clk Clock Manager Altera Corporation Send Feedback...
Page 492 FPGA-to-HPS bridge Clock for the GPV slave l4_mp_clk Lightweight HPS-to-FPGA bridge Clock for the GPV masters, and l4_mp_clk the data and GPV slave Clock for the control slave l4_mp_clk Quad SPI flash controller Clock Manager Altera Corporation Send Feedback...
Page 493 Clock for the SP timer 0 l4_sp_clk SP timer 1 Clock for the SP timer 1 l4_sp_clk I2C controller 0 Clock for the I2C 0 l4_sp_clk I2C controller 1 Clock for the I2C 1 Clock Manager Altera Corporation Send Feedback...
Page 494 Debounce clock gpio_db_clk Clock for the slave l4_mp_clk GPIO interface 2 Debounce clock gpio_db_clk System manager Clock for the system manager osc1_clk Clock for the control slave l4_sp_clk SDRAM subsystem Off-chip data clock ddr_dq_clk Clock Manager Altera Corporation Send Feedback...
Page 495 Trace port clock dbg_trace_clk Clock for the reset manager osc1_clk Reset manager Clock for the slave l4_sp_clk Scan manager Clock for the scan manager spi_m_clk Timestamp generator Clock for the timestamp generator dbg_timer_clk Clock Manager Altera Corporation Send Feedback...
Page 496: Clock Manager Address Map And Register Definitions
The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. • hps.html For more information, refer to this hps.html chapter of the Cyclone V Device Handbook. Document Revision History Table 2-10: Document Revision History Date...
Page 497: Reset Manager
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 498 • Debug reset • Occurs after HPS has already been through a cold reset • Used to recover debug logic from a non-responsive condition • Only affects the debug reset domain Reset Manager Altera Corporation Send Feedback...
Page 499: Reset Manager Block Diagram And System Integration
The reset signals from the HPS to the FPGA fabric must be synchronized to your user logic clock domain. Table 3-2: HPS External Reset Sources Source Description Cold reset request from FPGA fabric (active low) f2h_cold_rst_req_n Reset Manager Altera Corporation Send Feedback...
Page 500: Reset Controller
The reset controller generates module reset signals from external reset requests and internal reset requests. External reset requests originate from sources external to the reset manager. Internal reset requests originate from control registers in the reset manager. Reset Manager Altera Corporation Send Feedback...
Page 501: Module Reset Signals
• FPGA fabric Module Reset Signals The following table lists the module reset signals. The module reset signals are organized in groups for the MPU, peripherals, bridges, the level 3 (L3) interconnect, and miscellaneous. Reset Manager Altera Corporation Send Feedback...
Page 502 Resets quad SPI flash System qspi_flash_rst_n controller Resets each system watchdog System watchdog_rst_n[1:0] timer Resets each OSC1 timer System osc1_timer_rst_n[1:0] Resets each SP timer System sp_timer_rst_n[1:0] Resets each I2C controller System i2c_rst_n[3:0] Resets each UART System uart_rst_n[1:0] Reset Manager Altera Corporation Send Feedback...
Page 503 Description Reset Cold Warm Debug Software Domain Reset Reset Reset Deassert Resets boot ROM System boot_rom_rst_n Resets on-chip RAM System onchip_ram_rst_n Resets system manager System sys_manager_rst_n (resets logic associated with cold or warm reset) Reset Manager Altera Corporation Send Feedback...
Page 504 FPGA fabric Resets portion of TAP tap_cold_rst_n controller in the DAP that must be reset on a cold reset Resets SDRAM subsystem System sdram_cold_rst_n (resets logic associated with cold reset only) Reset Manager Altera Corporation Send Feedback...
Page 505: Slave Interface And Status Register
The use of the nPOR pin is optional and can be tied high when it is not required. Related Information Cyclone V Device Datasheet For information about the required duration of reset request signal assertion, refer to the Cyclone V Device Datasheet. Reset Manager...
Page 506: Reset Sequencing
(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins. (2) This dependency applies to all the reset signals. Reset Manager Altera Corporation Send Feedback...
Page 507 3. Wait for 96 cycles (so clocks can stabilize). 4. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link. Related Information Cold and Warm Reset Deassertion Sequence on page 3-12 Reset Manager Altera Corporation Send Feedback...
Page 508: Reset Pins
5. Wait for 32 cycles. Deassert mpu_clkoff for CPU0 and CPU1. 6. Peripherals remain held in reset until software brings them out of reset. Reset Pins Figure 3-5: Reset Pins SoC Device nTRST ARM DAP nPOR Reset Manager nRST rst_pin_rst_n Reset Manager Altera Corporation Send Feedback...
Page 509: Reset Effects
Related Information Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual For more information, refer to the individual chapters in the Cyclone V Device Handbook, Volume 3. Altering Warm Reset System Response Registers in the clock manager, system manager, and reset manager control how warm reset affects the HPS.
Page 510: Reset Handshaking
The base addresses of all modules are also listed in the Introduction to the Hard Processor System. Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 For more information, refer to Introduction to the Hard Processor System .
Page 511: Document Revision History
Minor formatting issues November 2012 • Added cold and warm reset timing diagrams. • Minor updates. May 2012 Added reset controller, functional description, and address map and register definitions sections. January 2012 Initial release. Reset Manager Altera Corporation Send Feedback...
Page 512: Interconnect
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 513: Interconnect Block Diagram And System Integration
(L4_SP, I4_sp_clk) (L4_OSC1, osc1_clk) System OSC1 Watchdog Clock Reset Scan UART Manager Timer (2) Manager Manager Manager Master (2) Timer (2) The L3 interconnect is a partially-connected switch fabric. Not all masters can access all slaves. Interconnect Altera Corporation Send Feedback...
Page 514 • FPGA Manager • HPS-to-FPGA Bridge • STM • Boot ROM • On-Chip RAM FPGA-to-HPS Bridge • L3 Slave Peripheral Switch • ACP ID Mapper Data • STM • On-Chip RAM • SDRAM Controller Subsystem L3 Data Interconnect Altera Corporation Send Feedback...
Page 515: L3 Masters
• Quad SPI flash Data slave interface connected to the L3 slave peripheral switch • FPGA manager Data slave interface connected to the L3 main switch • HPS-to-FPGA bridge Data slave interface connected to the L3 main switch Interconnect Altera Corporation Send Feedback...
Page 516: L3 Slaves
• STM Connected to the L3 main switch • Boot ROM Connected to the L3 main switch • On-chip RAM Connected to the L3 main switch • SDRAM controller subsystem SDRAM multi-port front end slave interface connected to the L3 main switch Interconnect Altera Corporation Send Feedback...
Page 517: L4 Slaves
• L4 main bus APB dedicated to the DMA and SPI slaves • DMA_s Access to the DMA controllers secure registers • DMA_ns Nonsecure access to the DMA controller nonsecure registers • SPI slave 0 CSR access • SPI slave 1 CSR access Interconnect Altera Corporation Send Feedback...
Page 518: Functional Description Of The Interconnect
• Lightweight HPS-to-FPGA Bridge • USB OTG 0/1 CSR • NAND CSR • NAND Command and Data • Quad SPI Flash Data • FPGA Manager • HPS-to-FPGA Bridge • STM • Boot ROM • On-Chip RAM Interconnect Altera Corporation Send Feedback...
Page 519 • HPS-to-FPGA Bridge • ACP ID Mapper Data • On-Chip RAM • SDRAM Controller Subsystem L3 Data USB OTG 0/1 • HPS-to-FPGA Bridge • ACP ID Mapper Data • On-Chip RAM • SDRAM Controller Subsystem L3 Data Interconnect Altera Corporation Send Feedback...
Page 520: Address Remapping
Each bit allows different combinations of address maps to be formed. There is only one remapping register available in the GPV, so modifying the remap register affects all memory maps of all the masters of the interconnect. Interconnect Altera Corporation Send Feedback...
Page 521 The effects of the remap bits can be categorized in the following groups: • MPU master interface • L2 cache master 0 interface • Non-MPU master interfaces • DMA master interface • Master peripheral interfaces • Debug Access Port (DAP) master interface • FPGA-to-HPS bridge master interface Interconnect Altera Corporation Send Feedback...
Page 522 1 MB of SDRAM. For non-MPU masters, either the on-chip RAM or the SDRAM maps to address 0x0. When mapped to address 0x0, the on-chip RAM obscures the lowest 64 K of SDRAM for non-MPU masters. Interconnect Altera Corporation Send Feedback...
Page 523: Master Caching And Buffering Overrides
The following masters have their caching and buffering signals driven by the system manager: • EMAC0 and EMAC1 • USB OTG 0 and USB OTG 1 • NAND flash • SD/MMC Interconnect Altera Corporation Send Feedback...
Page 524: Security
Cyclic Dependency Avoidance Schemes The AXI protocol permits re-ordering of transactions. As a result, when routing concurrent multiple transactions from a single point of divergence to multiple slaves, the interconnect might need to enforce rules to prevent deadlock. Interconnect Altera Corporation Send Feedback...
Page 525: Interconnect Master Properties
Interconnect Master Properties The interconnect connects to various slave interfaces through the L3 main switch and L3 slave peripheral switch. Interconnect Altera Corporation Send Feedback...
Page 526: Interconnect Slave Properties
Interconnect Slave Properties The interconnect connects to various slave interfaces through the L3 main switch, L3 slave peripheral switch, and the five L4 peripheral buses. After reset, all slave interfaces are set to the secure state. Interconnect Altera Corporation Send Feedback...
Page 527 2, 2, 2 spi_m_clk Lightweight HPS-to- L3 slave peripheral 16, 16, 32 2, 2, 2, 2, 2 l4_main_clk FPGA bridge switch USB OTG 0/1 L3 slave peripheral 1, 1, 1 2, 2, 2 usb_mp_clk switch Interconnect Altera Corporation Send Feedback...
Page 528: Upsizing Data Width Function
• OKAY is the lowest priority. Related Information infocenter.arm.com For more information about AXI terms such as DECERR, WRAP, and INCR, refer to the AMBA AXI Protocol Specification v1.0, which you can download from the ARM website. Interconnect Altera Corporation Send Feedback...
Page 529: Downsizing Data Width Function
The interconnect always converts WRAP bursts to WRAP bursts of twice the length, up to the output data width maximum size of WRAP16, and treats the WRAP burst as two INCR bursts that can each be converted into one or more INCR bursts. Interconnect Altera Corporation Send Feedback...
Page 530: Lock Support
The interconnect has one reset signal. The reset manager drives this signal to the SD/MMC controller on a cold or warm reset. On reset, the boot ROM is mapped to address 0x0. The DAP virtually maps to ID 2. Interconnect Altera Corporation Send Feedback...
Page 531: Interconnect Address Map And Register Definitions
Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter. • Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 4-6: Document Revision History Date...
Page 532: Hps-Fpga Axi Bridges
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 533: Axi Bridges Block Diagram And System Integration
(l4_mp_clk) (l4_mp_clk) (GPV) (GPV) HPS-to-FPGA FPGA-to-HPS Bridge Bridge Lightweight HPS-to-FPGA Bridge (GPV) 64 Bits 32 Bits 64 Bits (l3_main_clk) (l4_mp_clk) (l3_main_clk) (L3 Main Switch) (L3 Slave Peripheral Switch) (L3 Main Switch) L3 Interconnect HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 534: Functional Description Of The Axi Bridges
Interconnect on page 4-1 For more information about connectivity, such as which masters have access to each bridge, refer to the Interconnect chapter in the Cyclone V Device Handbook. Functional Description of the AXI Bridges The Global Programmers View The HPS-to-FPGA bridge includes a set of registers called the GPV. The GPV provides settings to control the bridge properties and behavior.
Page 535 2, 4, 6, 8, 10, 12, 14, or 128 bits 16 beats 64 bits 8 bytes 8 bytes 1 to 16 beats 128 bits 128 bits 8 or 16 bytes 8 or 16 bytes 1 to 16 beats 128 bits HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 536 4, 8, or 16 bits Input Write data strobes WSTRB 1 bit Input Write last data identifier WLAST 1 bit Input Write data channel valid WVALID 1 bit Output Write data channel ready WREADY HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 537 Read data RDATA 2 bits Output Read response RRESP 1 bit Output Read last data identifier RLAST 1 bit Output Read data channel valid RVALID 1 bit Input Read data channel ready RREADY HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 538: Hps-To-Fpga Bridge
It is critical to provide the correct l4_mp_clk clock to support access to the GPV, as described in GPV Clocks. The bridge master data width is user-configurable at the time you instantiate the HPS component in your system. HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 539 32, 64, or 128 Output Write data WDATA bits 4, 8, or 16 bits Output Write data strobes WSTRB 1 bit Output Write last data identifier WLAST 1 bit Output Write data channel valid WVALID HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 540 Table 5-14: HPS-to-FPGA Bridge Master Read Data Channel Signals Signal Width Direction Description 12 bits Input Read ID 32, 64, or 128 bits Input Read data RDATA 2 bits Input Read response RRESP 1 bit Input Read last data identifier RLAST HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 541: Lightweight Hps-To-Fpga Bridge
FPGA-to-HPS bridges, allow you to access the GPV registers for each bridge. The lightweight HPS-to-FPGA bridge also has a GPV to control the behavior of its four interfaces (one slave and three masters). The GPV is described in The Global Programmers View. HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 542 Table 5-17: Lightweight HPS-to-FPGA Bridge Master Write Data Channel Signals Signal Width Direction Description 12 bits Output Write ID 32 bits Output Write data WDATA 4 bits Output Write data strobes WSTRB 1 bit Output Write last data identifier WLAST HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 543 Read address channel ready ARREADY Table 5-20: Lightweight HPS-to-FPGA Bridge Master Read Data Channel Signals Signal Width Direction Description 12 bits Input Read ID 32 bits Input Read data RDATA 2 bits Input Read response RRESP HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 544: Clocks And Resets
For more information about the reset manager, refer to the Reset Manager chapter. • HPS Component Interfaces on page 28-1 For information about the f2h_axi_clk clock, refer to the HPS Component Interfaces chapter. HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 545: Data Width Sizing
You can set the bypass_merge bit in the GPV to prevent the bridge from merging data and responses. If the bridge merges multiple responses into a single response, that response is the one with the highest priority. The response types have the following priorities: HPS-FPGA AXI Bridges Altera Corporation Send Feedback...
Page 546: Hps-Fpga Axi Bridges Address Map And Register Definitions
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
Page 547: Cortex-A9 Microprocessor Unit Subsystem
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 548: Cortex-A9 Mpu Subsystem Block Diagram And System Integration
3 (L3) interconnect fabric or the SDRAM. L3 Interconnect MPU Subsystem (NIC-301) ARM Cortex-A9 MPCore Interrupts CPU0 CPU1 Debug Infrastructure ACP ID Mapper L2 Cache SDRAM Controller Subsystem Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 549: Cortex-A9 Mpu Subsystem Internals
Cortex-A9 MPU Subsystem Internals 2013.12.30 Cortex-A9 MPU Subsystem Internals This figure shows a block diagram of the Altera Cortex-A9 MPU subsystem. Cortex-A9 MPU Subsystem ARM Cortex-A9 MPCore CPU0 CPU1 (Dual-Core HPS Only) ARM Cortex-A9 Processor ARM Cortex-A9 Processor NEON Media SIMD...
Page 550: Cortex-A9 Mpu Subsystem Components
• Private watchdog timer for each processor core • Global timer • Interrupt controller Each transaction originating from the Altera Cortex-A9 MPU subsystem can be flagged as secure or nonsecure. Implementation Details Table 6-1: Cortex-A9 MPCore Processor Configuration This table shows the parameter settings for the Altera Cortex-A9 MPCore.
Page 551 • TrustZone security extensions • Configurable data endianness For a description of the parity error scheme and parity error signals, refer to the Cortex-A9 Technical Reference Manual, available on the ARM website (infocenter.arm.com). Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 552 • 38% faster than the original Thumb instruction set • The Thumb instruction set supported for legacy applications • Each processor core in the Altera HPS includes a memory management unit (MMU) to support the memory management requirements of common modern operating systems.
Page 553 NEON Multimedia Processing Engine The NEON multimedia processing engine (MPE) provides hardware acceleration for media and signal processing applications. Each ARM Cortex-A9 processor includes an ARM NEON MPE that supports SIMD processing. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 554 Memory Management Unit The MMU is used in conjunction with the L1 and L2 caches to translate virtual addresses used by software to physical addresses used by hardware. Each processor has a private MMU. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 555 The 1 MB boot region can be subsequently remapped to the bottom 1 MB of SDRAM region. Note: Alternatively, the boot region can be mapped to the 64 KB on-chip RAM. For more information, refer to the Interconnect chapter in the Cyclone V Device Handbook, Volume 3. Related Information The SDRAM Region...
Page 556 This region can start as low as 0xC0000000, depending on the L2 cache filter settings. The top of the FPGA slaves region is located at 0xFBFFFFFF. As a result, the size of the FPGA slaves region can range from 0 to 0x3F000000 bytes. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 557 The HPS peripherals region is the top 64 MB in the address space, starting at 0xFC000000 and extending to 0xFFFFFFFF. The HPS peripherals region is always allocated to the HPS dedicated peripherals for the Altera Cortex-A9 MPU subsystem. Performance Monitoring Unit Each Cortex-A9 processor has a Performance Monitoring Unit (PMU).
Page 558 For more information about the GIC, refer to the Interrupt Controller chapter of the Cortex-A9 MPCore Technical Reference Manual, available on the ARM website (infocenter.arm.com). Related Information • GIC Interrupt Map for the Cyclone V SoC HPS on page 6-12 The following table shows the interrupt map. •...
Page 559 6-13 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number CortexA9_0 Level cpu0_deflags4 CortexA9_0 Level cpu0_deflags5 CortexA9_0 Level cpu0_deflags6 CortexA9_1 Edge cpu1_parityfail CortexA9_1 Edge cpu1_parityfail_BTAC CortexA9_1 Edge cpu1_parityfail_GHB CortexA9_1...
Page 560 6-14 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number L2-Cache Edge l2_ecc_byte_wr_IRQ L2-Cache Edge l2_ecc_corrected_IRQ L2-Cache Edge l2_ecc_uncorrected_IRQ L2-Cache Level l2_combined_IRQ Level ddr_ecc_error_IRQ FPGA Level or Edge FPGA_IRQ0...
Page 561 6-15 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number FPGA Level or Edge FPGA_IRQ17 FPGA Level or Edge FPGA_IRQ18 FPGA Level or Edge FPGA_IRQ19 FPGA Level or Edge...
Page 562 6-16 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number FPGA Level or Edge FPGA_IRQ40 FPGA Level or Edge FPGA_IRQ41 FPGA Level or Edge FPGA_IRQ42 FPGA Level or Edge...
Page 563 6-17 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number FPGA Level or Edge FPGA_IRQ63 Level dma_IRQ0 Level dma_IRQ1 Level dma_IRQ2 Level dma_IRQ3 Level dma_IRQ4 Level dma_IRQ5 Level dma_IRQ6...
Page 564 6-18 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number USB0 Level usb0_IRQ USB0 Level usb0_ecc_corrected_IRQ USB0 Level usb0_ecc_uncorrected_IRQ USB1 Level usb1_IRQ USB1 Level usb1_ecc_corrected_IRQ USB1 Level usb1_ecc_uncorrected_IRQ CAN0...
Page 565 6-19 GIC Interrupt Map for the Cyclone V SoC HPS 2013.12.30 Source Block Interrupt Name Combined Triggering Interrupt Interrupts Number NAND Level nandw_ecc_uncorrected_IRQ NAND Level nande_ecc_corrected_IRQ NAND Level nande_ecc_uncorrected_IRQ QSPI Level qspi_IRQ QSPI Level qspi_ecc_corrected_IRQ QSPI Level qspi_ecc_uncorrected_IRQ (11)
Page 566 Interrupt Name column. Symbolic interrupt names are defined in a header file distributed with the source installation for your operating system. (13) This interrupt combines TIMINT1 and TIMINT2. (14) This interrupt combines the following interrupts: fpga_man_irq[7..0]. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 567 • Manages ACP access with cache coherency capabilities. For more information about the SCU, refer to the Snoop Control Unit chapter of the Cortex-A9 MPCore Technical Reference Manual, available on the ARM website (infocenter.arm.com). Related Information ARM Infocenter (www.infocenter.arm.com) Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 568 The high-bandwidth peripherals, including the FPGA data ports, connect to the L3 interconnect. Related Information • ACP ID Mapper on page 6-24 • Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port on page 6-22 Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 569 Note: Altera recommends that exclusive accesses bypass the ACP altogether, either through the 32-bit slave port of the SDRAM controller connected directly to the L3 interconnect or through the FPGA-to- SDRAM interface.
Page 570: Acp Id Mapper
IDs (0 and 1) are dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 support fixed and dynamic modes of operation while output ID 7 supports dynamic only. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 571 IDs in progress at any one time. The write acceptance of the ACP slave is five transactions, and the read acceptance is 13 transactions. Only four coherent read transactions per ID mapping can be outstanding at one time. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 572 ID. When the change is applied, the status register is updated. Software should check that the change has actually taken place by polling the corresponding status register. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 573 FPGA-to-HPS bridge to pass through to the ACP regardless of the user sideband value associated with the ID. (15) Values are in binary. The letter x denotes variable ID bits each master passes with each transaction. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 574: L2 Cache
• 512 KB total memory • Eight-way associativity • Physically addressed, physically tagged • Line length of 32 bytes • Critical first word linefills • Support for all AXI cache modes, as shown in Table 6-7. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 575 • Single event upset (SEU) protection • Parity on Tag RAM • ECC on L2 Data RAM For more information about SEU errors, refer to the System Manager chapter in the Cyclone V Device Handbook, Volume 3. • Two slave ports mastered by the SCU •...
Page 576 • FPGA soft IP using the ACP must only perform the following types of data writes: • 64-bit aligned in memory • 64 bit wide accesses For more information about SEU errors, refer to the System Manager chapter in the Cyclone V Device Handbook, Volume 3. Related Information...
Page 577 Table 6-9: L2 Cache Events Event Description Eviction (cast out) of a line from the L2 cache. DRHIT Data read hit in the L2 cache. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 578 In addition, the L2 cache events can be captured and timestamped using dedicated debugging circuitry. For more information about L2 event capture, refer to the Debug chapter of the Cortex-A9 MPCore Technical Reference Manual, available on the ARM website (infocenter.arm.com). Related Information ARM Infocenter (www.infocenter.arm.com) Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 579: Debugging Modules
For information about global timestamps, refer to the CoreSight Debug and Trace chapter in the Cyclone V Device Handbook, Volume 3. • Target addresses for direct branches For more information about the PTM, refer to the CoreSight PTM-A9 Technical Reference Manual, available on the ARM website (infocenter.arm.com). Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 580: Cortex-A9 Mpu Subsystem Register Implementation
For an address map of peripheral slave ports, including the SCU and L2 cache, refer to the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. For detailed definitions of the registers for the Altera Cortex-A9 MPU subsystem, refer to the Cortex-A9 MPCore Technical Reference Manual, and the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Revision r3p2, available on the ARM website (infocenter.arm.com).
Page 581: Document Revision History
December 2013 2013.12.30 Correct SDRAM region address in MPCore Address Map November 2012 Minor updates. May 2012 • Add description of the ACP ID mapper • Consolidate redundant information January 2012 Initial release. Cortex-A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback...
Page 582: Coresight Debug And Trace
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 583: Arm Coresight Documentation
• CoreSight Trace Memory Controller Technical Reference Manual, ARM DDI 0461B Related Information Info center For more information, refer to the CoreSight Components Technical Reference Manual and the CoreSight Technology System Design Guide. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 584: Coresight Debug And Trace Block Diagram And System Integration
CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the performance of a complete HPS design. CoreSight technology addresses the requirement for a multicore debug and trace solution with high bandwidth for whole systems beyond the processor core. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 585: Debug Access Port (Dap)
FPGA to insert messages into the trace stream. When the STM detects a rising edge on an event pin, a message identifying the event is inserted into the stream. The lower four event pins (3:0) are connected to csCTI. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 586: Trace Funnel
8-bit HPS I/O interface and a 32-bit interface to the FPGA fabric. The trace data sent to the FPGA fabric can be transported off-chip using available serializer/deserializer (SERDES) resources in the FPGA. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 587: Embedded Cross Trigger (Ect) System
2, it only enters and exits through trigger inputs and outputs you configure. Trigger Outputs Trigger Inputs Channel Interface Channel Channel Interface Interface Channel 0 Channel 1 Trigger Trigger Channel 2 Interface Interface Channel 3 Channel Interface Trigger Interface CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 588 The two CTMs are connected together, allowing triggers to be transmitted between the MPU debug subsystem, the debug system, and the FPGA fabric. Each CTM has four ports and each port has four channels. Each CTM port can be connected to a CTI or another CTM. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 589 Cross Trigger Matrix (CTM) 2013.12.30 Figure 7-4: CTM Channel Structure The following figure shows the structure of a CTM channel. Paths inside the CTM are purely combinatorial. Channel 0 CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 590: Program Trace Macrocell (Ptm)
The HPS contains two PTMs. Each PTM is paired with a processor and CTI. Trace data generated from the PTM can be transmitted off-chip using HPS pins, or to the FPGA fabric, where it can be pre-processed and transmitted off-chip using high-speed FPGA pins. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 591: Hps Debug Apb Interface
28-1 CoreSight Debug and Trace Programming Model This section describes programming model details specific to Altera’s implementation of the ARM CoreSight technology. The debug components can be configured to cause triggers when certain events occur. For example, soft logic in the FPGA fabric can signal an event which triggers an STM message injection into the trace stream.
Page 592: Stm Channels
Each STM message contains a master ID that tells the host debugger which master is associated with the message. The STM master ID is determined by combining a portion of the AWADDRS signal and the AWPROT protection bit. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 593: Fpga Interface
• 0 - System APB port read from DAP • 1 - System APB Port write to DAP The STM has 28 event pins, f2h_stm_hw_events[28], for FPGA to trigger events to STM. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 594 Note: When the FPGA is powered down or not configured, the TPIU sends the lower 8-bits trace data to I/Os. h2f_tpiu_clock_in Clock from the FPGA used to capture trace data. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 595: Cti Trigger Connections To Outside The Debug System
ACQCOMP FULL Table 7-9: csCTI Trigger Output Signals The following table lists the trigger output pin connections implemented for csCTI. Number Signal Destination TRIGIN FLUSHIN HWEVENTS[3:2] HWEVENTS[1:0] TPIU TRIGIN TPIU FLUSHIN TRIGIN CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 596: Configuring Embedded Cross-Trigger Connections
3. This configuration causes a trigger at trigger input 0 in FPGA-CTI to propagate to trigger output 3 in the FPGA-CTI and trigger output 7 in CTI-0. Propagation can be single-to-single, single-to-multiple, multiple- to-single, and multiple-to-multiple. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 597: Debug Clocks
Cross trigger matrix clock for CTM. It can CTMCLK(for CTM) mpu_clk manager be synchronous or asynchronous to CTICLK. Clock DAP internal clock. It must be equivalent DAPCLK dbg_clk manager to PCLKDBG. Clock Debug APB (DAPB) clock. PCLKDBG dbg_clk manager CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 598: Debug Resets
SoC-provided reset signal that resets all of the AMBA HRESETn sys_dbg_rst_ on-chip interconnect. Use this signal to reset the DAP AHB-Lite master port. Reset manager Resets system APB slave port of DAP. PRESETSYSn sys_dbg_rst_ CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 599: Coresight Debug And Trace Address Map And Register Definitions
ARM documentation. The register addresses are offsets relative to the base address of each module instance. Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter. CoreSight Debug and Trace...
Page 600: Document Revision History
Table 7-13: Document Revision History Date Version Changes December 2013 2013.12.30 Maintenance release. November 2012 Minor updates. June 2012 Added functional description, programming model, and address map and register definitions sections. January 2012 Initial release. CoreSight Debug and Trace Altera Corporation Send Feedback...
Page 601: Sdram Controller Subsystem
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 602: Sdram Controller Subsystem Interfaces
SDRAM interface timing. Related Information Memory Controller Architecture on page 8-4 SDRAM Controller Subsystem Interfaces The following sections describe the SDRAM controller subsystem interfaces. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 603 • Each Avalon-MM or AXI interface of the FPGA-to-HPS SDRAM interface operates on an independent clock domain. • The FPGA-to-HPS SDRAM interfaces are configured during FPGA configuration. The following table shows the number of ports needed to configure different bus protocols, based on type and data width. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 604: Memory Controller Architecture
The SDRAM controller consists of an MPFE, a single-port controller, and an interface to the CSRs. The following figure shows a block diagram of the SDRAM controller portion of the SDRAM controller subsystem. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 605: Multi-Port Front End
FIFO buffers and clock boundary crossing for the write data. The write data block informs the command block of the amount of pending write data for each transaction so that the command block can calculate eligibility for the next SDRAM write burst. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 606: Singleport Controller
Each SDRAM burst read or write is converted to the appropriate Altera PHY interface (AFI) command to open a bank on the correct row for the transaction (if required), execute the read or write command, and precharge the bank (if required).
Page 607: Functional Description Of The Sdram Controller Subsystem
The scheduler recognizes eight priority levels (0-7), with higher values representing higher priorities. For example, any transaction with priority seven is scheduled before transactions of priority six or lower. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 608: Mpfe Sdram Burst Scheduling
If the bank is not idle, other operations to that bank yield until the high-priority operation is finished. If the chip select, row, and column fields match an earlier transaction, the high-priority transaction yields until the earlier transaction is completed. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 609: Singleport Sdram Controller Operational Behavior
SDRAM bursts or by the extended command interface. When a bank must be reallocated, the least-recently-used open bank is used as the replacement. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 610: Write Combining
Hamming logic to detect and correct single-bit errors and detect double-bit errors. The controller ECC is available for 16-bit and 32-bit widths, each requiring an additional 8 bits of memory, resulting in an actual memory width of 24-bits and 40-bits, respectively. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 611: Interleaving Options
When an ECC error occurs, an interrupt signal notifies the MPU subsystem, and the ECC error information is stored in the status registers. Interleaving Options The controller supports the following address-interleaving options: • Noninterleaved • Bank interleave without chip select interleave • Bank interleave with chip select interleave SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 612 This interleaving allows smaller data structures to spread across multiple banks and chips (giving access to 16 total banks for multithreaded access to blocks of memory). Memory timing is degraded when switching between chips. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 613: Axi-Exclusive Support
Address_ Points to a 1MB block and is the lower address. Incoming addresses match if they are greater than or equal to this value. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 614: Example Of Configuration For Trustzone
Table 8-5: Rules in Memory Protection Table for Example Configuration Rule # Port Mask TID Low TID High Address Low Address High Prot Fail/Allow 0’b1111111111 4095 allow 0’b1111111111 4095 2047 allow SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 615: Sdram Power Management
SDRAM burst-scheduling queue is empty for a specified number of clock cycles. The SDRAM automatically reactivates when an active SDRAM command is received. Other power-down modes are performed only under user control. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 616: Ddr Phy
In terms of clock relationships, the FPGA fabric connects the appropriate clocks to write data, read data, and command ports for the constructed ports. Related Information Clock Manager on page 2-1 SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 617: Resets
Avalon-MM Read Port, and AXI port. Avalon-MM Bidirectional Port The Avalon-MM bidirectional ports are standard Avalon-MM ports used to dispatch read and write operations. Each configured Avalon-MM bidirectional port consists of the signals listed in the following table. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 618 Information about the Avalon-MM protocol Avalon-MM Write Port The Avalon-MM write ports are standard Avalon-MM ports used only to dispatch write operations. Each configured Avalon-MM write port consists of the signals listed in the following table. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 619 Information about the Avalon-MM protocol Avalon-MM Read Port The Avalon-MM read ports are standard Avalon-MM ports used only to dispatch read operations. Each configured Avalon-MM read port consists of the signals listed in the following table. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 620 The AXI port uses an AXI-3 interface. Each configured AXI port consists of the signals listed in the following table. Each AXI interface signal is independent of the other interfaces for all signals, including clock and reset. Table 8-11: AXI Port Signals Name Bits Direction Function Reset ARESETn Clock ACLK SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 621 8 bit wide transfer for 32-bit wide to 256-bit wide transfer. Last transfer in a burst WLAST Indicates write data+strobes are valid WVALID Indicates ready for write data and strobes WREADY SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 622 Read Address Channel Signals Read identification tag ARID Read address ARADDR Read burst length ARLEN Width of the transfer size ARSIZE Burst type ARBURST Indicates ready for a read command ARREADY Indicates valid read command ARVALID SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 623: Sdram Controller Subsystem Programming Model
Therefore, the memory interface must be configured with the correct PHY-level timing information. Although configuration of the memory interface in Qsys is still necessary, it is limited to PHY- and board-level settings. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 624: Hps Memory Interface Configuration
You should add a stage to your testbench to assert and deassert the H2F reset in the HPS. Appropriate Verilog code is shown below: initial begin // Assert reset <base name>.hps.fpga_interfaces.h2f_reset_inst.reset_assert(); // Delay SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 625: Generating A Preloader Image For Hps With Emif
.sof creating a preloader image. Note: You must regenerate the hardware handoff files whenever the HPS configuration changes; for example, due to changes in Peripheral Pin Multiplexing or I/O standard for HPS pins. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 626: Creating A Preloader Bsp File
To enable semihosting in the Preloader, follow these steps: 1. When you create the file in the BSP Editor, turn on SEMIHOSTING in the spl.debug window to .bsp enable semihosting. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 627: Enabling Simple Memory Test
To enable the simple memory test, follow these steps: 1. When you create the file in the BSP Editor, turn on HARDWARE_DIAGNOSTIC in the spl.debug .bsp window to enable the simple memory test. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 628 SDRAM memory size, open the file <design folder>\ spl_bsp uboot-socfpga include configs socfpga_ in a text editor, and change the PHYS_SDRAM_1_SIZE parameter at line 292 to specify your cyclone5.h actual memory size in bytes. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 629: Enabling The Debug Report
2. Locate the line #define RUNTIME_CAL_REPORT 0 and change it to #define RUNTIME_CAL_REPORT 1. Figure 8-7: Semihosting Printout With Debug Support Enbled Analysis of Debug Report The following analysis will help you interpret the debug report. SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 630 The Write Deskew, Read Deskew, DM Deskew, and Read after Write results are reported in delay steps (nominally 25ps, in Arria V and Cyclone V devices), not in picoseconds. For more information about calibration, refer to Calibration Stages in the Functional Description—UniPHY chapter, in the External Memory Interface Handbook.
Page 631: Writing A Predefined Data Pattern To Sdram In The Preloader
= 0; //counter to loop different data pattern num_address; num_address=50; data_temp[0]=0XFFFFFFFE; //initial data for walking 0 pattern data_temp[1]=0X00000001; //initial data for walking 1 pattern SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 632 (cnt = (0+i*num_address); cnt < ((i+1)*num_address) ; cnt = cnt++ addr = base + cnt; /* pointer arith! */ sync (); read_data=*addr; printf("Address:%X Expected: %08X Read:%08X \n",addr, expected_data[i],read_data); if (expected_data[i] !=read_data) { puts("!!!!!!FAILED!!!!!!\n\n"); hang(); expected_data[i]=ROTATE_RIGHT(expected_data[i]); ====//End Of Code//===== SDRAM Controller Subsystem Altera Corporation Send Feedback...
Page 633: Sdram Controller Address Map And Register Definitions
Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 Base addresses of all HPS modules • Cyclone V SoC HPS Address Map and Register Definitions Register and field descriptions for all HPS modules Document Revision History Date Version...
Page 634: On-Chip Memory
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 635: On-Chip Ram Block Diagram And System Integration
The on-chip RAM reset is driven by the onchip_ram_rst_n interconnect reset signal. Related Information • Clock Manager on page 2-1 For more information about the operating frequency and maximum throughput, refer to the Clock Manager chapter. • Reset Manager on page 3-1 On-Chip Memory Altera Corporation Send Feedback...
Page 636: Boot Rom
(MPU) subsystem, MPU0 executes the pre-bootloader code stored in the boot ROM. The boot ROM uses an 32-bit slave interface. The slave interface supports transfers between memory and the NIC-301 L3 interconnect. All writes return an error response. On-Chip Memory Altera Corporation Send Feedback...
Page 637: On-Chip Memory Address Map And Register Definitions
The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. • Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 9-1: Document Revision History...
Page 638 Document Revision History 2013.12.30 Date Version Changes January 2012 Initial release. On-Chip Memory Altera Corporation Send Feedback...
Page 639: Nand Flash Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 640: Functional Description Of The Nand Flash Controller
To support booting and initialization, the rdy_busy_in pin must be connected. The NAND flash controller sends the reset command to the connected device. NAND Flash Controller Altera Corporation Send Feedback...
Page 641: Bootstrap Interface
The following table lists the relevant bootstrap setting bits, found in the system manager’s bootstrap register, in the nandgrp group. This table also lists recommended bootstrap settings for a 512 byte page device. NAND Flash Controller Altera Corporation Send Feedback...
Page 642: Configuration By Host
When this register is set, the NAND flash controller expects the host to program the related device parameter registers. For more information, refer to Configuration by Host. (18) All registers are in the config group. NAND Flash Controller Altera Corporation Send Feedback...
Page 643: Clocks
Clock for the NAND flash controller nand_clk The frequency of nand_x_clk is four times the frequency of nand_clk. For more information about the clock inputs, refer to the Clock Manager chapter in the Cyclone V Device Handbook, Volume 3. Resets The NAND flash controller has one reset signal, nand_flash_rst_n.
Page 644: Command Mapping
Using this abstraction layer provides enhanced performance. Commands take multiple cycles to send off-chip. The MAP commands let you initiate commands and let the flash controller sequence them off-chip to the NAND device. NAND Flash Controller Altera Corporation Send Feedback...
Page 645 Data width-aligned buffer address on the memory BUFF_ADDR device. Maximum page access is 8 KB. (reserved) Set to 0 MAP00 Usage Limitations The usage of this command under normal operations is limited to the following situations: NAND Flash Controller Altera Corporation Send Feedback...
Page 646 MAP01 Address Mapping Table 10-4: MAP01 Address Mapping Address Bits Name Description 31:28 (reserved) Set to 0 27:26 Set to 1 CMD_MAP 25:24 (reserved) Set to 0 (19) 23:<M> Block address in the device BLK_ADDR NAND Flash Controller Altera Corporation Send Feedback...
Page 647 . Therefore, use the following values: 32 pages per block: <M>=5 64 pages per block: <M>=6 128 pages per block: <M>=7 256 pages per block: <M>=8 384 pages per block: <M>=9 512 pages per block: <M>=9 NAND Flash Controller Altera Corporation Send Feedback...
Page 648 . Therefore, use the following values: 32 pages per block: <M>=5 64 pages per block: <M>=6 128 pages per block: <M>=7 256 pages per block: <M>=8 384 pages per block: <M>=9 512 pages per block: <M>=9 NAND Flash Controller Altera Corporation Send Feedback...
Page 649 The host can issue only single-beat accesses to the data slave port while using MAP11 commands. Related Information MAP11 Addressing Mapping on page 10-12 NAND Flash Controller Altera Corporation Send Feedback...
Page 650: Data Dma
With certain restrictions, non-DMA MAP10 commands can be issued to the NAND flash controller while the flash controller is servicing DMA transactions. MAP00, MAP01, and MAP11 commands cannot be issued while DMA mode is enabled because the flash controller is operating in an extremely tightly-coupled, NAND Flash Controller Altera Corporation Send Feedback...
Page 651 Command-Data Pair Formats. Related Information Command-Data Pair Formats on page 10-13 Command-Data Pair Formats Related Information • Indexed Addressing on page 10-5 • Burst DMA Command on page 10-15 NAND Flash Controller Altera Corporation Send Feedback...
Page 652 512 pages per block: <M>=9 (22) The buffer address in host memory, which must be aligned to 32 bits. (23) The buffer address in host memory, which must be aligned to 32 bits. NAND Flash Controller Altera Corporation Send Feedback...
Page 653 DMA transfer. INT can take on one of the following values: 0 Do not interrupt host. The dma_cmd_comp bit is set to 0. 1 Interrupt host. The dma_cmd_comp bit is set to 1. NAND Flash Controller Altera Corporation Send Feedback...
Page 654: Command Dma
You can optionally send the 16-bit fields in the above table to the NAND flash controller as four separate bursts of length 1 in sequential order. Altera recommends this method. If you want the NAND flash controller DMA to perform cacheable accesses then you must configure the cache bits by writing the l3master register in the nandgrp group in the system manager.
Page 655 10-17 Multitransaction Command-DMA Command Format The following tables show the format of each command-data pair for multi-transaction DMA commands. Table 10-9: Transaction 1 Address Encoding 31:28 27:26 25:24 23:0 Res. Reserved NAND Flash Controller Altera Corporation Send Feedback...
Page 656 The flash controller ignores out-of-order DMA commands. If transactions are not in the expected order, the flash controller resets itself to the initial state and generates an un_sup interrupt. Any other transactions in between command-DMA MAP10 commands cause the flash controller to ignore the command-DMA NAND Flash Controller Altera Corporation Send Feedback...
Page 657 MAP10 command-DMA command. Related Information NAND Reset Commands on page 10-23 DMA Command Descriptor The command descriptor consists of the pointer to the current command as well as pointer to the next descriptor. NAND Flash Controller Altera Corporation Send Feedback...
Page 658 The flash controller updates this field when the command operation is completed. Sync flag pointer Address of sync buffer Sync arguments Arguments controlling the buffer sync mechanism Related Information • Command Flags Field Description on page 10-21 • Status Fields on page 10-21 NAND Flash Controller Altera Corporation Send Feedback...
Page 659 Continue bit. Fail When set, denotes that operation failed to complete successfully. 13:12 Reserved Reserved NAND Flash Controller Altera Corporation Send Feedback...
Page 660 When set to one, the type is to increment the sync buffer flag and the value 23:16 is ignored. The Increment is to read the current value of the flag, increment it by one, and store the sync buffer flag. NAND Flash Controller Altera Corporation Send Feedback...
Page 661 Sync status is updated if the command is received while waiting for the flash operation to complete. If this command is received while DMA channel is performing sync update, the channel finishes the sync update before idling. NAND Flash Controller Altera Corporation Send Feedback...
Page 662: Ecc
ECC information is striped in between 512 or 1024 bytes of data across the page. The NAND flash controller reads ECC information in the same pattern and the presence of errors is calculated according to 512 or 1024 bytes of data read. NAND Flash Controller Altera Corporation Send Feedback...
Page 663 The NAND flash controller does not introduce or interpret ECC check bits in spare area transfer mode, and acts as pass through for data transfer. Figure 10-3: Spare Area Transfer Mode Programming Model for ECC Sector 3 ECC3 Flags NAND Flash Controller Altera Corporation Send Feedback...
Page 664 The host writes both the data sectors and the bad block markers. The flash controller depends on the host software to set up the bad block markers properly before writing the data. For more information about the formatting of this data, refer to Main+Spare Area Transfer Mode. NAND Flash Controller Altera Corporation Send Feedback...
Page 665: Interface Signals
The host can take corrective action after the number of correctable errors encountered reaches a particular threshold value. Interface Signals Table 10-18: NAND Flash Interface Signals Signal Width Description in/out Command, address and data for the flash device Address latch enable NAND Flash Controller Altera Corporation Send Feedback...
Page 666: Nand Flash Controller Programming Model
If you write a configuration register and follow it up with a data operation that is dependent on the value of this configuration register, Altera recommends that you read the value of the register before performing the data operation. This read operation ensures that the posted write of the register is completed and takes effect before the data operation is issued to the NAND flash controller.
Page 667 • If the device implements multiplane address restrictions, set the flag bit in the multiplane_addr_restrict register to 1. • Initialize the die_mask and first_block_of_next_plane registers as per device requirements. NAND Flash Controller Altera Corporation Send Feedback...
Page 668 3. Enable DMA if your application needs DMA mode. Enable DMA by setting the flag bit of the dma_enable register in the dma group. Altera recommends that the software reads back this register to ensure that the mode change is accepted before sending a DMA command to the flash controller.
Page 669 Set the following registers in the config group to optimize the NAND flash controller for the speed grade of the connected device and frequency of operation of the flash controller: • twhr2_and_we_2_re • tcwaw_and_addr_2_data • re_2_we • acc_clks • rdwr_en_lo_cnt • rdwr_en_hi_cnt • max_rd_delay • cs_setup_cnt • re_2_re NAND Flash Controller Altera Corporation Send Feedback...
Page 670: Flash-Related Special Function Operations
If the erase operation fails on any of the blocks in a multi-plane erase command, an erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group. NAND Flash Controller Altera Corporation Send Feedback...
Page 671 The NAND flash controller determines the default transfer mode from the setting of transfer_spare_reg register in the config group. Use MAP10 commands to dynamically change the transfer mode from the existing mode to the new mode. All subsequent commands are in the new mode NAND Flash Controller Altera Corporation Send Feedback...
Page 672 1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the target block. (27) Default access mode (0x42) maps to either main (only) or main+spare mode, depending on the value of transfer_spare_reg. NAND Flash Controller Altera Corporation Send Feedback...
Page 673 • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the same destination address. • Write 0x62 to the Data register. This step performs the write. NAND Flash Controller Altera Corporation Send Feedback...
Page 674 The NAND flash controller cannot do ECC validation in case of copy-back commands. The flash controller copies the ECC data, but does not check it during the copy operation. Altera recommends that you use copy- back only if the ECC implemented in the flash controller is strong enough so that the next access can correct accumulated errors.
Page 675 The same four-entry queue is used to queue the address and page count for pipeline read-ahead and write-ahead commands. This commonality requires that you use MAP01 commands to read out all pages for a pipeline read-ahead command before the next pipeline command can be processed. NAND Flash Controller Altera Corporation Send Feedback...
Page 676 Set Up a Single Area for Pipeline Read-Ahead To set up an area for pipeline read-ahead, perform the following steps: NAND Flash Controller Altera Corporation Send Feedback...
Page 677: Nand Flash Controller Address Map And Register Definitions
The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. NAND Flash Controller...
Page 678: Document Revision History
Document Revision History 2013.12.30 Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 • Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 10-20: Document Revision History Date Version Changes December 2013 2013.12.30...
Page 679: Sd/Mmc Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 680: Sd Card Support Matrix
Where supported, controls the voltage switch output to support 1.8-V signalling for SD. (30) SPI mode is obsolete in the MMC 4.41 specification. (31) Supports a maximum clock rate of 50 MHz instead of 52 MHz (specified in MMC specification). SD/MMC Controller Altera Corporation Send Feedback...
Page 681: Sd/Mmc Controller Block Diagram And System Integration
Storage FIFO Buffer Interrupt Control Subsystem Functional Description of the SD/MMC Controller This section describes the SD/MMC controller components and how the controller operates. (30) SPI mode is obsolete in the MMC 4.41 specification. SD/MMC Controller Altera Corporation Send Feedback...
Page 682: Sd/Mmc/Ce-Ata Protocol
The BIU interfaces with the CIU, and is connected to the level 3 (L3) interconnect and level 4 (L4) peripheral buses. The BIU consists of the following primary functional blocks, which are defined in the following sections: SD/MMC Controller Altera Corporation Send Feedback...
Page 683 • If the wait_prvdata_complete bit is 0, the new command is sent to the SD/MMC/CE-ATA card as soon as the previous command is sent. Typically, use this feature to stop or abort a previous data † transfer or query the card status in the middle of a data transfer. SD/MMC Controller Altera Corporation Send Feedback...
Page 684 (ECCs). Both interfaces to the FIFO buffer support single and double bit error injection. The enable and error injection pins are inputs driven by the system manager and the status pins are outputs driven to the MPU subsystem. SD/MMC Controller Altera Corporation Send Feedback...
Page 685 Data Buffer 2 The Distance Between 2 Data Buffer 1 Descriptors Is Determined Descriptor B by the DSL Value Programmed in the BMOD Register Data Buffer 2 Data Buffer 1 Descriptor C Data Buffer 2 SD/MMC Controller Altera Corporation Send Feedback...
Page 686 DMA controller. When this bit is set to 0, it indicates that the descriptor is owned by the host. The internal DMA controller resets this bit to 0 when it completes the data transfer. SD/MMC Controller Altera Corporation Send Feedback...
Page 687 Reserved The DES1 descriptor field contains the buffer size. † Table 11-5: Internal DMA Controller DES1 Descriptor Field Bits Name Description 31:26 Reserved SD/MMC Controller Altera Corporation Send Feedback...
Page 688 (fb) of the bmod register. The maximum burst length is indicated and limited by the programmable burst length (pbl) field of the bmod register. When descriptors are being fetched, the † master interface always presents a burst size of four to the interconnect. SD/MMC Controller Altera Corporation Send Feedback...
Page 689 The final interrupt signal from the controller is a logical OR of the interrupts from the BIU and internal DMA controller. Internal DMA Controller FSM The following steps show the internal DMA controller finite state machine (FSM) operations: SD/MMC Controller Altera Corporation Send Feedback...
Page 690 For a card read abort, the internal DMA controller reads the data out of the FIFO buffer and writes † them to the corresponding descriptor data buffers. The remaining unread descriptors are not closed. SD/MMC Controller Altera Corporation Send Feedback...
Page 691 A fatal bus error occurs due to an error response through the master interface. This error is a system error, so the software driver must not perform any further setup on the controller. The only recovery mechanism † from such scenarios is to perform one of the following tasks: SD/MMC Controller Altera Corporation Send Feedback...
Page 692: Ciu
CE-ATA transfers. † The CIU consists of the following primary functional blocks: † • Command path † • Data path † • Clock control Command Path † The command path performs the following functions: SD/MMC Controller Altera Corporation Send Feedback...
Page 693 After a new command is loaded in the command path (the update_clock_registers_only bit in † the cmd register is set to 0), the command path state machine sends out a command on the card bus. SD/MMC Controller Altera Corporation Send Feedback...
Page 694 1 in the rintsts register. The command path verifies the contents of the card response. † Table 11-9: Card Response Fields Field Contents Response transmission bit Command index Command index of the sent command End bit SD/MMC Controller Altera Corporation Send Feedback...
Page 695 † and to send the CCSD pattern on the command line. † 2. Receive the CCS on the CMD line. † • Send CCSD command Sends the CCSD pattern (0b00001) on the CMD line. SD/MMC Controller Altera Corporation Send Feedback...
Page 696 I/O transmission delay is applicable for read transfers using the RW_REG and RW_BLK commands; the RW_REG and RW_BLK commands used in this document refer to the RW_MULTIPLE_REGISTER and † RW_MULTIPLE_BLOCK MMC commands defined by the CE-ATA specification. SD/MMC Controller Altera Corporation Send Feedback...
Page 697 SD/SDIO STOP command. A stream data transfer is terminated when the end bit of the STOP command and end bit † of the data match over two clock cycles. SD/MMC Controller Altera Corporation Send Feedback...
Page 698 If the block size is less than 4, 16, or 32 for card data widths of 1 bit, 4 bits, or 8 bits, respectively, the data transmit state machine terminates the data transfer when all the data is transferred, at which time the † internally-generated STOP command is loaded in the command path. SD/MMC Controller Altera Corporation Send Feedback...
Page 699 CRC-16 is separately generated and checked for 1, 4, or 8 data lines, respectively. If there is a CRC-16 mismatch, the data path signals a data CRC error to the BIU. If the received end bit is not 1, the † BIU receives an End-bit Error (EBE). SD/MMC Controller Altera Corporation Send Feedback...
Page 700 MMC, and a multiple-block read or write for SD memory transfer for SD cards. The software must set the send_auto_stop bit according to the † following details: † The following list describes conditions for the AUTO_STOP command: SD/MMC Controller Altera Corporation Send Feedback...
Page 701 Stream write Open-ended stream Stream write >0 Auto-stop after all bytes transfer Single-block read >0 Byte count = 0 is illegal Single-block write >0 Byte count = 0 is illegal Multiple-block read Open-ended multiple block SD/MMC Controller Altera Corporation Send Feedback...
Page 702 2) Issue CMD18/CMD25 commands without issuing CMD23 command to the card, with the send_auto_stop bit set. In this case, the multiple-block data transfer is terminated by an internally- † generated auto-stop command after the programmed byte count. SD/MMC Controller Altera Corporation Send Feedback...
Page 703 The clock frequency of a card depends on the following clock ctrl register settings: (33) Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and † the MMC specification. SD/MMC Controller Altera Corporation Send Feedback...
Page 704 CRC-7. • Response error response transmission bit is not 0, command index does not match with the command † index of the send command, or response end bit is not 1. SD/MMC Controller Altera Corporation Send Feedback...
Page 705: Clocks
(hto) in rintsts register to 1, and the data path continues to wait for the FIFO buffer to empty. Clocks Table 11-14: SD/MMC Controller Clocks Clock Name Direction Description Clock for SD/MMC controller BIU l4_mp_clk Clock for SD/MMC controller sdmmc_clk Generated output clock for card sdmmc_cclk_out Internal Divide-by-four clock of sdmmc_clk sdmmc_clk_divided SD/MMC Controller Altera Corporation Send Feedback...
Page 706 Related Information • Clock Setup Refer to this section for information about setting the phase shift. • Clock Control Block on page 11-25 Refer to this section for information about the generation of the sdmmc_cclk_outclock. SD/MMC Controller Altera Corporation Send Feedback...
Page 707: Resets
After the power and clock to the controller are stable, the controller active-low reset is asserted. The reset sequence initializes the registers, FIFO buffer pointers, DMA interface controls, and state machines in the † controller. SD/MMC Controller Altera Corporation Send Feedback...
Page 708 † 4. Set the int_enable bit of the ctrl register to 1. Note: Altera recommends that you write 0xFFFFFFFF to the rintsts register to clear any pending † interrupts before setting the int_enable bit to 1. 5. Discover the card stack according to the card type. For discovery, you must restrict the clock frequency to 400 kHz in accordance with SD/MMC/CE-ATA standards.
Page 709 1. Reset the card width 1 or 4 bit (card_width2) and card width 8 bit (card_width1) fields in the ctype register to 0. 2. Identify the card type as SD, MMC, SDIO or SDIO-COMBO: SD/MMC Controller Altera Corporation Send Feedback...
Page 710 You must issue the SEND_IF_COND command prior to the first SD_SEND_OP_COND command, to initialize the High Capacity SD memory card. The card returns busy as a response to the SD_SEND_OP_COND command when any of the following conditions are true: SD/MMC Controller Altera Corporation Send Feedback...
Page 711 • For an MMC, send the following command sequence: • GO_IDLE_STATE • SEND_OP_COND (CMD1) • ALL_SEND_CID • SEND_RELATIVE_ADDR 7. You can change the card clock frequency after discovery by writing a value to the clkdiv register that divides down the sdmmc_clk clock. SD/MMC Controller Altera Corporation Send Feedback...
Page 712 9. Set the clkdiv register of the controller to the correct divider value for the required clock frequency. 10. Set the cclk_enable bit of the clkena register to 1, to enable the card clock generation. SD/MMC Controller Altera Corporation Send Feedback...
Page 713: Controller/Dma/Fifo Buffer Reset Usage
Ensure that the DMA is idle before performing a DMA reset. Otherwise, the L3 interconnect might † be left in an indeterminate state. Altera recommends setting the controller_reset, fifo_reset, and dma_reset bits in the ctrl register to 1 first, and then resetting the rintsts register to 0 using another write, to clear any resultant interrupt.
Page 714 1 or 0 Choose the value based on the speed mode being use_hold_reg used. Indicates that the command is not a clock update update_clk_regs_only command Indicates that the command is not a data command data_expected SD/MMC Controller Altera Corporation Send Feedback...
Page 715: Data Transfer Commands
Before sending a command on the command line, wait_prvdata_complete the host must wait for completion of any data command already in process. Altera recommends that you set this bit to 1, unless the current command is to query status or stop data transfer when transfer is in progress.
Page 716 (cardthrctl) to ensure that the card clock does not stop in the middle of a block of data being transferred from the card to the host. For more information, refer † to Card Read Threshold. SD/MMC Controller Altera Corporation Send Feedback...
Page 717 8. When a DTO interrupt is received, the software must read the remaining data from the FIFO buffer. † Figure 11-12: Command Argument for IO_RW_EXTENDED (CMD53) Command Index R/W/Flag Function Number Block Mode OP code Register address Byte/Block Count SD/MMC Controller Altera Corporation Send Feedback...
Page 718 Read from card read_write 1 for R2 (long) response response_length 0 for short response 1 or 0 0 for commands with no response, such as SD/ response_expect SDIO GO_IDLE_STATE, SET_DSR, and GO_ INACTIVE_STATE. 1 otherwise SD/MMC Controller Altera Corporation Send Feedback...
Page 719 • Data starvation by the host the controller wrote data to the card faster than the host could supply † the data. † In both cases, the software must write data into the FIFO buffer. † There are two types of transfers: open-ended and fixed length. SD/MMC Controller Altera Corporation Send Feedback...
Page 720 STATE etc. † Table 11-20: cmd Register Settings for Single-Block and Multiple-Block Write (User Selectable) Parameter Value Comment 0 Sends command to the CIU immediately wait_prvdata_complete 1 Sends command after previous data transfer ends SD/MMC Controller Altera Corporation Send Feedback...
Page 721 † READ_MULTIPLE_BLOCK or WRITE_MULTIPLE_BLOCK command) † • READ_MULTIPLE_BLOCK multiple-block read command † • WRITE_MULTIPLE_BLOCK multiple-block write command † Packed commands are organized in packets by the application software and are transparent to the controller. SD/MMC Controller Altera Corporation Send Feedback...
Page 722: Transfer Stop And Abort Commands
1. Set the cmdarg register to include the appropriate command argument parameters listed in cmdarg † Register Settings for SD/SDIO ABORT Command. † 2. Send the IO_RW_DIRECT command by setting the following fields of the cmd register: SD/MMC Controller Altera Corporation Send Feedback...
Page 723: Internal Dma Controller Operations
This section describes the internal DMA controller’s initialization process, and transmission sequence, and reception sequence. Internal DMA Controller Initialization † To initialize the internal DMA controller, perform the following steps: † 1. Set the required bmod register bits: SD/MMC Controller Altera Corporation Send Feedback...
Page 724 DMA transfer, the change has no effect. Disabling only takes effect for a new data transfer command. • Issuing a software reset immediately terminates the transfer. Prior to issuing a software reset, Altera recommends the host reset the DMA interface by setting the dma_reset bit of the ctrl register †...
Page 725: Commands For Sdio Card Devices
The SUSPEND and RESUME operations are implemented by writing to the appropriate bits in the CCCR (Function 0) of the SDIO card. To read from or write to the CCCR, use the controller’s IO_RW_DIRECT † command. SD/MMC Controller Altera Corporation Send Feedback...
Page 726 Bit values are listed in the following table. † Table 11-22: cmdarg Bit Values for RESUME Command Bits Content Value R/W flag 30:28 Function number 0, for CCCR access RAW flag 1, read after write Don't care SD/MMC Controller Altera Corporation Send Feedback...
Page 727 1. Check if the card supports the read_wait facility by reading the SDIO card’s SRW bit, bit 2 at offset 0x8 † in the CCCR. 2. If this bit is 1, all functions in the card support the read_wait facility. Use the SD/SDIO IO_RW_DIRECT † command to read this bit. SD/MMC Controller Altera Corporation Send Feedback...
Page 728: Ce-Ata Data Transfer Commands
The host processor then writes the address and byte count to the cmdarg † register before setting the cmd register bits. † For the RW_REG command, there is no CCS from the CE-ATA card device. SD/MMC Controller Altera Corporation Send Feedback...
Page 729 Table 11-24: cmd Register Settings for ATA Task File Transfer Value Comment start_cmd CCS is not expected ccs_expected 0 or 1 Set to 1 if RW_BLK or RW_REG read read_ceata_device No clock parameters update command update_clk_regs_only card_num SD/MMC Controller Altera Corporation Send Feedback...
Page 730 FIFO buffer. Implementing ATA Payload Transfer † To implement an ATA payload transfer (read or write), perform the following steps: † 1. Write the data size in bytes to the bytcnt register. SD/MMC Controller Altera Corporation Send Feedback...
Page 731 Block transfer mode. Byte count must be integer transfer_mode multiple of 4kB. Block size can be 512, 1k or 4k bytes 1 or 0 1 for write and 0 for read read_write Data is expected data_expected response_length response_expect SD/MMC Controller Altera Corporation Send Feedback...
Page 732 1 when the controller is set to send the CCSD pattern, the controller sends the internally-generated STOP command to the CMD pin. After sending the STOP command, the controller † sets the acd bit in the rintsts register to 1. SD/MMC Controller Altera Corporation Send Feedback...
Page 733 The host issues a RW_REG command for the ATA command, and the data is retrieved with the RW_BLK † command. The host controller uses the following settings while sending a RW_REG command for the IDENTIFY † DEVICE ATA command. The following list shows the primary bit settings: SD/MMC Controller Altera Corporation Send Feedback...
Page 734 SD/SDIO CMD39 or RW_REG command. Only the status field of the ATA task file † contains the success status; there is no error status. The host controller uses the following settings while sending the RW_REG command for the STANDBY † IMMEDIATE ATA command: SD/MMC Controller Altera Corporation Send Feedback...
Page 735: Card Read Threshold
RX FIFO buffer before the controller † enables the card clock. † The card read threshold is required when the round trip delay is greater than half of sdmmc_clk_divided. SD/MMC Controller Altera Corporation Send Feedback...
Page 736 Delay_R > 0.5 * (sdmmc_clk/4) Delay_R < 0.5 * (sdmmc_clk/4) Related Information Cyclone V Device Datasheet Recommended Usage Guidelines for Card Read Threshold † 1. The cardthrctl register must be set before setting the cmd register for a data read command.
Page 737 Table 11-32: Legal Values of dw_dma_multiple_transaction_size and rx_wmark for Block Size = 512 Block Size dw_dma_multiple_transaction_size rx_wmark Card Read Threshold Programming Examples † This section shows examples of how to program the card read threshold. SD/MMC Controller Altera Corporation Send Feedback...
Page 738: Interrupt And Error Handling
1, the controller tries to load the command. If the command buffer already contains a command, this error is raised, and the new command is discarded, † requiring the software to reload the command. SD/MMC Controller Altera Corporation Send Feedback...
Page 739: Booting Operation For Emmc And Mmc
• JEDEC Standard No. 84-A44 • JEDEC Standard No. JESD84-A43 Related Information www.jedec.org For more information about this boot method, refer to the following JEDEC Standards available on the JEDEC website: No. 84-A441, No. 84-A44, and No. JESD84-A43. SD/MMC Controller Altera Corporation Send Feedback...
Page 740 † set to 0. Note: Altera recommends that you write 0xFFFFFFFF to the rintsts and idsts registers to clear any pending interrupts before setting the int_enable bit. For internal DMA controller † mode, the software driver needs to unmask all the relevant fields in the idinten register.
Page 741 Within 0.95 seconds of the Boot ACK Received interrupt, the Boot Data Start interrupt must be received from the controller. If this does not occur, the software driver must write the following cmd † register fields: SD/MMC Controller Altera Corporation Send Feedback...
Page 742 If the Boot Data Start interrupt is not received from the controller within 1 second of initiating the † command (step 9), the software driver must write the cmd register with the following fields: SD/MMC Controller Altera Corporation Send Feedback...
Page 743 † must: † 1. Discover these cards as it would discover MMC4.0/4.1/4.2 cards for the first time † 2. Know the card characteristics † 3. Decide whether to perform a boot operation or not SD/MMC Controller Altera Corporation Send Feedback...
Page 744 • JEDEC Standard No. 84-A44 • JEDEC Standard No. JESD84-A43 Related Information www.jedec.org For more information about alternative boot operation, refer to the following JEDEC Standards available on the JEDEC website: No. 84-A441, No. 84-A44, and No. JESD84-A43. SD/MMC Controller Altera Corporation Send Feedback...
Page 745 • Sets the int_enable bit of the ctrl register to 1. Other bits in the ctrl register must be set to † Note: Altera recommends writing 0xFFFFFFFF to the rintsts register and idsts register to clear any pending interrupts before setting the int_enable bit. For internal DMA controller †...
Page 746 Within 0.95 seconds of the Boot ACK Received interrupt, the Boot Data Start interrupt must be received from the controller. If this does not occur, the software driver must discontinue the boot † process and start with normal discovery. SD/MMC Controller Altera Corporation Send Feedback...
Page 747 If the Boot Data Start interrupt is not received from the controller within 1 second of initiating the command (step 11), the software driver must discontinue the boot process and start with normal † † discovery. In internal DMA controller mode: SD/MMC Controller Altera Corporation Send Feedback...
Page 748 Thus, the controller must: † 1. Discover these cards as it would discover MMC4.0/4.1/4.2 cards for the first time † 2. Know the card characteristics † 3. Decide whether to perform a boot operation or not SD/MMC Controller Altera Corporation Send Feedback...
Page 749: Voltage Switches
(i.e. switching between 1.8V and 3.3V). However, for the HPS (or Altera device), the I/O pins are connected to the SD/MMC card running at 3.3V. If your card runs at 1.8V, the voltage-translation transceiver is needed for voltage translation between the HPS and the SD/MMC card.
Page 750: Sd/Mmc Controller Address Map And Register Definitions
The address map and register definitions reside in the hps.html file that accompanies this handbook volume. 1. To view the module description and base address: a. Click the link provided below to open the Address Map Information for Cyclone V SoC HPS file b. Scroll to and click the sdmmc link 2.
Page 751 Document Revision History 2013.12.30 Date Version Changes November 2012 • Added programming model section. • Reorganized programming information. • Added information about ECCs. • Added pin listing. • Updated clocks section. January 2012 Initial release SD/MMC Controller Altera Corporation Send Feedback...
Page 752: Quad Spi Flash Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 753: Quad Spi Flash Controller Block Diagram And System Integration
• DMA peripheral request controller issues requests to the DMA peripheral request interface to communicate with the external DMA controller • SPI PHY serially transfers data and commands to the external SPI flash devices Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 754: Functional Description Of The Quad Spi Flash Controller
An external master, for example a processor, triggers the direct access controller with a read or write operation to the data slave interface. The data slave exposes a 1 MB window into the flash device. You can remap this window to any 1 MB location within the flash device. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 755: Indirect Access Mode
The address of the read access must be in the indirect address range. You can configure the indirect address through the indaddrtrig register. The external master can issue 32-bit reads until Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 756 The external master can issue 32-bit writes until the last word of an indirect transfer. On the final write, the external master may issue a 32-bit, 16-bit or 8-bit Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 757: Local Memory Buffer
SRAM partition register (srampart), based on 32-bit word sizes. For example, to specify four bytes of storage, write the value 1. The value written to the indirect read partition size field (addr) defines the number Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 758: Dma Peripheral Request Controller
DMA burst or single request. When the SRAM fill level falls below the watermark level, the transfer watermark reached interrupt is generated. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 759: Stig Operation
Note: Altera recommends using the STIG instead of the SPI legacy mode to access the flash device registers and perform erase operations. SPI Legacy Mode SPI legacy mode allows software to access the internal TX FIFO and RX FIFO buffers directly, thus bypassing the direct, indirect and STIG controllers.
Page 760: Configuring The Flash Device
Opcode Send Address Send Data Value Value Read Fast read Dual output fast read (DOFR) Dual I/O fast read (DIOFR) Quad output fast read (QOFR) Quad I/O fast read (QIOFR) Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 761: Xip Mode
When the enterxipnextrd or enterxipimm bit of the cfg register is set to 0, the quad SPI controller and flash device exit XIP mode on the next read instruction. For more information, refer to the XIP Mode Operations” section. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 762: Write Protection
When the access is detected as nonsequential, the sequential access to the flash device is terminated and a new sequential access begins. Altera recommends accessing the data slave sequentially. Sequential access has less command overhead, and therefore, increases data throughput.
Page 763: Interrupts
TX FIFO full This condition occurs only in legacy SPI mode. When 0, the TX FIFO buffer is not full. When 1, the TX FIFO buffer is full. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 764: Interface Signals
Active low slave select 0 ss_n[0] Active low slave select 1 ss_n[1] Active low slave select 2 Single, dual, or quad Output ss_n[2] Active low slave select 3 ss_n[3] Serial clock sclk Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 765: Quad Spi Flash Controller Programming Model
6. If the watermark level is used, set the SRAM watermark level through the indrdwater register. 7. Start the indirect read operation by setting the start field of the indrd register to 1. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 766: Indirect Read Operation With Dma Enabled
7. Start the indirect write operation by setting the start field of the indwr register to 1. 8. Either use the watermark level interrupt or poll the SRAM fill level in the sramfill register to determine when there is sufficient space in the SRAM. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 767: Indirect Write Operation With Dma Enabled
2. Disable the direct access controller and indirect access controller to ensure no new read or write accesses are sent to the flash device. 3. Set the XIP mode bits in the modebit register to 0x80. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 768 1. Disable the direct access controller and indirect access controller to ensure no new read or write accesses are sent to the flash device. 2. Restore the mode bits to the values before entering XIP mode, depending on the flash device and manufacturer. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 769: Quad Spi Flash Controller Address Map And Register Definitions
Quad SPI Flash Controller Address Map and Register Definitions The address map and register definitions reside in the Address Map Information for Cyclone V SoC HPS file that accompanies this handbook volume. Click the link, below, to open the file.
Page 770 2013.12.30 Date Version Changes November 2012 Minor updates. May 2012 Added block diagram and system integration, functional descrip- tion, programming model, and address map and register definitions sections. January 2012 Initial release. Quad SPI Flash Controller Altera Corporation Send Feedback...
Page 771: Fpga Manager
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 772: Fpga Manager Block Diagram And System Integration
• Control controls the FPGA CB. • Monitor monitors the configuration signals in the FPGA CB and sends interrupts to the MPU subsystem. • Fabric I/O reads and writes signals from or to the FPGA fabric. FPGA Manager Altera Corporation Send Feedback...
Page 773: Functional Description Of The Fpga Manager
• Rising edge • Falling edge © Note: Portions 2013 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any FPGA Manager Altera Corporation Send Feedback...
Page 774: Fpga Configuration
The FPGA manager supports a data width of 32 or 16 bits. When configuring the FPGA fabric from the HPS, Altera recommends that you always set the data width to 32 bits. For partial reconfiguration, the 16-bit data width is the only option.
Page 775 Configuration, Design Security, and Remote System Upgrades For more information about configuring the FPGA through the HPS, refer to the Configuration, Design Security, and Remote System Upgrade appendix in the Cyclone V Device Handbook, Volume 1. (36) Other MSEL values are allowed when the FPGA is configured from a non-HPS source. For information, refer to the Configuration, DesignSecurity, and Remote System Upgrades in the Cyclone V Device Handbook, Volume 1.
Page 776 Related Information • Booting and Configuration For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration appendix in the Cyclone V Device Handbook, Volume 3. • Booting and Configuration Introduction on page 30-1 For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration appendix.
Page 777: Clock
Configuration, Design Security, and Remote System Upgrades For more information about configuring the FPGA through the HPS, refer to the Configuration, Design Security, and Remote System Upgrade appendix in the Cyclone V Device Handbook, Volume 1. • Booting and Configuration For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration appendix in the Cyclone V Device Handbook, Volume 3.
Page 778: Reset
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 • Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 13-2: Document Revision History Date Version Changes December 2013 2013.12.30...
Page 779: System Manager
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 780: System Manager Block Diagram And System Integration
• Register slave interface provides connected masters access to the CSRs in the system manager. • Watchdog debug pause accepts the debug mode status from the MPU subsystem and pauses the L4 watchdog timers. System Manager Altera Corporation Send Feedback...
Page 781: Functional Description Of The System Manager
CPU0 booted from. Related Information • Booting and Configuration For boot and clock source values, refer to the Booting and Configuration appendix in the Cyclone V Device Handbook, Volume 3. • Booting and Configuration Introduction on page 30-1 For boot and clock source values, refer to the Booting and Configuration appendix.
Page 782 Register bits should be accessed only when the master interface is guaranteed to be in an inactive state. Related Information • Clock Manager on page 2-1 • Ethernet Media Access Controller on page 17-1 System Manager Altera Corporation Send Feedback...
Page 783 When CPU1 is released from reset and the boot ROM code is located at the CPU1 reset exception address (for a typical case), the boot ROM reset handler code reads the address stored in the CPU1 start address register (cpu1startaddr) and passes control to software at that address. System Manager Altera Corporation Send Feedback...
Page 784: Fpga Interface Enables
The global interface bit (intf) of the global disable register (gbl) disables all interfaces between the FPGA and HPS. Note: Ensure that all interfaces between the FPGA and HPS are inactive before disabling them. System Manager Altera Corporation Send Feedback...
Page 785: Ecc And Parity Control
HPS hardware. When the operating system kernel boots, it retrieves the information by reading the preloader to OS handoff information register array. These registers are reset only by a cold reset. System Manager Altera Corporation Send Feedback...
Page 786: Clocks
Related Information • Introduction to the Hard Processor System The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. • hps.html Document Revision History...
Page 787 14-9 Document Revision History 2013.12.30 Date Version Changes January 2012 Initial release. System Manager Altera Corporation Send Feedback...
Page 788: Scan Manager
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 789: Scan Manager Block Diagram And System Integration
Register Slave Interface L4 Peripheral Bus (osc1_clk) Note: Not all devices contain all the banks depicted. The processor accesses the scan manager through the register slave interface connected to the level 4 (L4) peripheral bus. Scan Manager Altera Corporation Send Feedback...
Page 790 OUT field of the CSW register (the trst bit of the stat register in the scan manager) has an effect only when port 7 is enabled by software. For details, refer to Communicating with the JTAG TAP Controller section. Scan Manager Altera Corporation Send Feedback...
Page 791 CONFIG_IO mode is commonly used to configure the I/O pin properties prior to performing boundary scan testing. Related Information • Configuring HPS I/O Scan Chains on page 15-5 • Communicating with the JTAG TAP Controller on page 15-6 Scan Manager Altera Corporation Send Feedback...
Page 792: Functional Description Of The Scan Manager
15-8 • System Manager The HPS I/O pins need to be frozen before configuring them. For more information, refer to the System Manager chapter in the Cyclone V Device Handbook, Volume 3. • System Manager on page 14-1 The HPS I/O pins need to be frozen before configuring them.
Page 793: Communicating With The Jtag Tap Controller
Before connecting or disconnecting the scan chain between the scan manager and the FPGA JTAG TAP controller, ensure that both the FPGA JTAG TCK and scan manager TCK signals are de-asserted. Altera recommends resetting the FPGA JTAG TAP controller using the scan manager's nTRST signal after the scan manager is connected to the controller.
Page 794: Clocks
Because glitches can happen on the output clocks during a warm reset, the scan manager temporarily stops generation of the JTAG-AP and I/O configuration clocks. This action ensures that a warm reset does not cause output clock glitches. Scan Manager Altera Corporation Send Feedback...
Page 795: Scan Manager Address Map And Register Definitions
JTAG-AP Register Name Cross Reference Table To improve clarity regarding how Altera uses the JTAG-AP, the ARM register names are changed in the SoC device. The following table cross references the ARM and Altera names.
Page 796: Document Revision History
Changes December 2013 2013.12.30 Minor formatting issues November 2012 Added JTAG-AP descriptions. May 2012 Added block diagram and system integration, functional descrip- tion, and address map and register definitions sections. January 2012 Initial release. Scan Manager Altera Corporation Send Feedback...
Page 797: Dma Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 798 • Single and double bit ECC support • Supports 31 peripheral request interfaces: • 8 for FPGA • 8 for I • 8 for SPI • 2 for quad SPI • 1 for System Trace Macrocell • 4 for UART DMA Controller Altera Corporation Send Feedback...
Page 799: Dma Controller Block Diagram And System Integration
The DMAC contains an instruction processing block that processes program code that controls a DMA transfer. The program code is stored in a region of system memory that the DMAC accesses using its AXI master interface. The DMAC stores instructions temporarily in an internal cache. DMA Controller Altera Corporation Send Feedback...
Page 800: Operating States
The following figure shows the transitions among operating states for the DMA manager thread and DMA channel threads. The DMAC provides a separate state machine for each thread. The DMAC provides a separate state machine for each thread. DMA Controller Altera Corporation Send Feedback...
Page 801 Executing state by all of the following: • DMA manager thread Issuing the DMAGO instruction through the slave interface • DMA channel thread Programming the DMA manager thread to execute DMAGO for a DMA channel thread in the Stopped state DMA Controller Altera Corporation Send Feedback...
Page 802 Waiting For Peripheral A DMA channel thread is stalled and the DMAC is waiting for the peripheral to provide the requested data. After the peripheral provides the data, the thread returns to the Executing state. DMA Controller Altera Corporation Send Feedback...
Page 803: Error Checking And Correction
The boot_manager_ns signal is the only method to set the security state of the DMA manager. When the DMAC exits from reset, it reads the status of the boot_manager_ns signal and sets the security of the DMA manager. DMA Controller Altera Corporation Send Feedback...
Page 804 Related Information Security Usage on page 16-18 Describes the effect of the security state of the peripheral request interfaces on the execution of the DMAWFP, DMALDP, DMASTP, or DMAFLUSHP instructions by a DMA channel thread. DMA Controller Altera Corporation Send Feedback...
Page 805: Using The Slave Interfaces
3. Program one of the slave interfaces on the DMAC to a DMAGO instruction as follows: a. Poll the DBGSTATUS register to ensure that debug is idle, and the dbgstatus bit is 0 b. Write to the DBGINST0 register and enter all of the following: DMA Controller Altera Corporation Send Feedback...
Page 806: Peripheral Request Interface
The DMAC supports 31 peripheral request handshakes. Each request handshake can receive up to four outstanding requests, and is assigned a specific peripheral device ID. The following table lists the peripheral device ID assignments. DMA Controller Altera Corporation Send Feedback...
Page 807 The peripheral controls the DMA cycle in one of the following ways: • Selects a single transfer • Selects a burst transfer • Notifies the DMAC when it commences the final request in the current series DMA Controller Altera Corporation Send Feedback...
Page 808 The DMAC controls the total amount of data. The peripheral uses the peripheral request interface to notify the DMAC when it requires the DMAC to transfer data to or from the peripheral. The DMA channel thread controls how the DMAC responds to the peripheral requests. DMA Controller Altera Corporation Send Feedback...
Page 809 Note: The CCRn register controls how much data is transferred for a burst request and a single request. Altera recommends that you do not update a CCRn register when a transfer is in progress for channel n. • After the peripheral sends a burst request, the peripheral must not send a single request until the DMAC acknowledges that the burst request is complete.
Page 810: Using Events And Interrupts
If the DMAC executes DMASEV before another channel executes DMAWFE the event remains pending until the DMAC executes DMAWFE. When the DMAC executes DMAWFE it halts execution for one aclk clock cycle, clears the event and then continues execution of the channel thread. DMA Controller Altera Corporation Send Feedback...
Page 811: Aborts
• Precise AbortThe DMAC updates the PC register with the address of the instruction that created the abort. • Imprecise AbortThe PC register might contain the address of an instruction which did not cause the abort to occur. DMA Controller Altera Corporation Send Feedback...
Page 812 • Store queue is empty. • All of the running channels are prevented from executing a DMALD instruction either because the MFIFO buffer does not have sufficient free space or another channel owns the load-lock. DMA Controller Altera Corporation Send Feedback...
Page 813 Program Thread Has an Abort Has an Abort Occurred? Occurred? Thread Moves to the Faulting Completing State Active AXI Transactions Complete? Thread Moves to the Faulting State DMAKILL Executed? Thread Moves to the Stopped State DMA Controller Altera Corporation Send Feedback...
Page 814: Security Usage
• Peripheral request interfaces The PNS bit in the CR4 register returns the security state of these interfaces. Additionally, each DMA channel thread contains a dynamic non-secure bit, CNS, that is valid when the channel is not in the Stopped state. DMA Controller Altera Corporation Send Feedback...
Page 815 • Sets the mgr_evnt_err bit in the FTRD register. • Moves the DMA manager to the Faulting state. • If INS = 1 The event-interrupt resource is in the Non-secure state. The DMAC creates the event interrupt. DMA Controller Altera Corporation Send Feedback...
Page 816 When a DMA channel thread is in the Secure state, it enables the DMAC to perform secure and non-secure AXI accesses. DMA Channel Thread in Non-Secure State When the CNS bit is 1, the DMA channel thread is programmed to operate in the Non-secure state and it only performs non-secure instruction fetches. DMA Controller Altera Corporation Send Feedback...
Page 817 • Moves the DMA channel to the Faulting completing state. • If PNS = 1 The peripheral is in the Non-secure state. The DMAC sends a message to the peripheral to communicate when the data transfer is complete. DMA Controller Altera Corporation Send Feedback...
Page 818: Constraints And Limitations Of Use
The AXI specification does not permit AXI bursts to cross 4 KB address boundaries. If you program the DMAC with a combination of burst start address, size, and length that would cause a single burst to cross DMA Controller Altera Corporation Send Feedback...
Page 819: Programming Restrictions
If you update any of endian_swap_size, SARn , or DARn , for example, using a DMAADDH SAR instruction, then you must ensure that the SARn and DARn registers contain an address aligned to the size that the endian_swap_size field specifies before executing any additional DMALD or DMAST instructions. DMA Controller Altera Corporation Send Feedback...
Page 820 A discontinuity occurs if you change any of the following: • src_inc bit. • src_burst_size field. • SAR register so that it modifies the source byte lane alignment. Because the bus width is 64 bits, you change bits [2:0] in the SAR register. DMA Controller Altera Corporation Send Feedback...
Page 821 To avoid DMAC lockup, the total MFIFO buffer requirement of the set of channel programs must be equal to or less than 512, the MFIFO buffer depth. Related Information • Watchdog Abort on page 16-16 DMA Controller Altera Corporation Send Feedback...
Page 822: Dma Controller Programming Model
• Spaces To separate items, single spaces are used for clarity. When a space is obligatory in the assembler syntax, two or more consecutive spaces are used. DMA Controller Altera Corporation Send Feedback...
Page 823: Instruction Set Summary
DMAST Store DMAST[S | B] on page 16-38 DMASTP Store and Notify DMASTP<S | B> on page Peripheral 16-39 DMASTZ Store Zero DMASTZ on page 16-40 DMAWFE Wait For Event DMAWFE on page 16-40 DMA Controller Altera Corporation Send Feedback...
Page 824: Instructions
32-bit addition. The DMAC discards the carry bit so that addresses wrap from 0xFFFFFFFF to 0x00000000. The net effect is to subtract between 65536 and 1 from the current value in the source or destination address register. DMA Controller Altera Corporation Send Feedback...
Page 825 You can use the instruction with the DMA manager thread and the DMA channel thread. DMAFLUSHP Flush Peripheral clears the state in the DMAC that describes the contents of the peripheral and sends a message to the peripheral to resend its level status. DMA Controller Altera Corporation Send Feedback...
Page 826 DMAGO <channel_number>, <32- bit_immediate> [, ns] where: <channel_number> Selects a DMA channel. It must be one of: C0 DMA channel 0 C1 DMA channel 1 C2 DMA channel 2 C3 DMA channel 3 C4 DMA channel 4 DMA Controller Altera Corporation Send Feedback...
Page 827 You can use the instruction with the DMA manager thread and the DMA channel thread. Note: You must not use the DMAKILL instruction in DMA channel programs. To issue a DMAKILL instruction, use the DBGINST0 register. DMA Controller Altera Corporation Send Feedback...
Page 828 It places the read data into a FIFO buffer that is tagged with the corresponding channel number and after it receives the last data item, it sends an acknowledgement DMA Controller Altera Corporation Send Feedback...
Page 829 The DMAC saves the value of the PC for the instruction that follows DMALP. After the DMAC executes DMALPEND, and the loop counter register is not zero, this enables it to execute the first instruction in the loop. DMA Controller Altera Corporation Send Feedback...
Page 830 DMALP. • 1 The DMAC executes a DMANOP and therefore exits the loop. Figure 16-14: DMALPEND[S|B] Instruction Encoding 4 3 2 1 backwards_jump[7:0] bs x Assembler syntax DMALPEND[S|B] DMA Controller Altera Corporation Send Feedback...
Page 831 • 0 if the loop counter 0 registers contains the loop counter value • 1 if the loop counter 1 registers contains the loop counter value • 1 if DMALPFE started the program loop. Operation DMA Controller Altera Corporation Send Feedback...
Page 832 • SAR selects the source address registers and sets rd to b000 • CCR selects the channel control registers and sets rd to b001 • DAR selects the destination address registers and sets rd to b010 DMA Controller Altera Corporation Send Feedback...
Page 833 This enables write-after-read sequences to the same address location with no hazards. Figure 16-17: DMARMB Instruction Encoding 6 5 4 3 2 1 0 Assembler syntax DMARMB Operation You can only use this instruction in a DMA channel thread. DMA Controller Altera Corporation Send Feedback...
Page 834 DMAC updates the destination address registers after it executes DMAST[S|B]. Figure 16-19: DMAST[S|B] Instruction Encoding 6 5 4 3 2 1 Assembler syntax DMAST[S|B] DMA Controller Altera Corporation Send Feedback...
Page 835 DMAC updates the destination address registers after it executes DMASTP<S|B>. Figure 16-20: DMASTP<S|B> Instruction Encoding 11 10 9 8 7 6 5 4 3 2 1 0 periph[4:0] Assembler syntax DMA Controller Altera Corporation Send Feedback...
Page 836 Wait For Event instructs the DMAC to halt execution of the thread until the event, that <event_num> specifies, occurs. When the event occurs, the thread moves to the Executing state and the DMAC clears the event. DMA Controller Altera Corporation Send Feedback...
Page 837 <burst> Sets bs to 1 and p to 0. This instructs the DMAC to continue executing the DMA channel thread after it receives a burst DMA request. The DMAC sets the request_type to Burst. DMA Controller Altera Corporation Send Feedback...
Page 838: Assembler Directives
Assembler directive to place a 32-bit immediate in the instruction stream. Syntax DCD imm32 Assembler directive to place an 8-bit immediate in the instruction stream. Syntax DCB imm8 DMALP Assembler directive to insert an iterative loop. Syntax DMA Controller Altera Corporation Send Feedback...
Page 839 Source address increment. Sets the value of I = Increment arburst[0] F = Fixed Source burst size in bits. Sets the value of 8, 16, 32, or 64 arsize[2:0] Source burst length. Sets the value of arlen[3:0] 1 to 16 DMA Controller Altera Corporation Send Feedback...
Page 840: Mfifo Buffer Usage Overview
Because the DMAC ties ARCACHE[3] LOW, the assembler always sets bit 3 to 0 and uses bits [2:0] of your chosen value for SC. (41) Because the DMAC ties AWCACHE[2] LOW, the assembler always sets bit 2 to 0 and uses bit [3] and bits [1:0] of your chosen value for DC. DMA Controller Altera Corporation Send Feedback...
Page 841 The following program shows the MFIFO buffer usage. In this program, the source address and destination address are aligned with the AXI data bus width. DMAMOV CCR, SB4 SS64 DB4 DS64 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4000 DMALP 16 DMALD shown as a in figure below DMALPEND DMAEND DMA Controller Altera Corporation Send Feedback...
Page 842 Data for DMAST DMAST This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four MFIFO buffer entries. DMA Controller Altera Corporation Send Feedback...
Page 843 DMALD ; shown as a1, ... a, an in the figure below DMAST ; shown as b in the figure below DMALPEND DMAMOV CCR, SB4 SS64 DB1 DS32 DMAST ; shown as c in the figure below DMAEND DMA Controller Altera Corporation Send Feedback...
Page 844 DMAST ; shown as c in the figure below DMALPEND DMAMOV CCR, SB1 SS32 DB4 DS64 DMALD ; shown as d in the figure below DMAST ; shown as e in the figure below DMAEND DMA Controller Altera Corporation Send Feedback...
Page 845 DMALD ; shown as c and cn in the figure below DMALPEND DMAMOV CCR, SB3 SS64 DB4 DS64 DMALD ; shown as e in the figure below DMAMOV CCR, SB1 SS32 DB4 DS64 DMALD ; shown as f in the figure below DMA Controller Altera Corporation Send Feedback...
Page 846 MFIFO buffer width. DMAMOV CCR, SB4 SS32 DB4 DS32 DMAMOV SAR, 0x1000 DMAMOV DAR, 0x4004 DMALP 16 DMALD ; shown as a in the figure below DMAST ; shown as b in the figure below DMA Controller Altera Corporation Send Feedback...
Page 847 Data for DMAST DMAST This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four MFIFO buffer entries. DMA Controller Altera Corporation Send Feedback...
Page 848: Dma Controller Registers
The following DMAC register map spans a 4 KB region, consists of the following sections. Figure 16-33: DMAC Summary Register Map 0xFFF Component ID 0xFE0 0xE14 Configuration 0xE00 0xD0C Debug 0xD00 0x4FC AXI and Loop Counter Status 0x400 0x13C DMA Channel Thread Status 0x100 0x05C Control 0x000 DMA Controller Altera Corporation Send Feedback...
Page 849: Address Map And Register Definitions
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
Page 850: Ethernet Media Access Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 851: Phy Interface
• Option to pass all multicast addressed frames • Promiscuous mode support to pass all frames without any filtering for network monitoring • Passes all incoming packets (as per filter) with a status report Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 852: Emac Block Diagram And System Integration
RGMII transmit data. The data bus changes with both rising and falling edges of the transmit clock (clk_tx_i). The validity of the data is qualified with phy_txen_o. Synchronous to: clk_tx_i, clk_tx_180_i Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 853 This is the reference clock to the EMAC. The clock is emac0_clk or emac1_clk supplied by the clock manager. The system manager drives the phy_intf_sel signal to control which clock is used. The clock rate is 250 MHz. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 854: Emac To Fpga Phy Interface
PHY Transmit Data Enable: This signal is driven by the EMAC component and has the following function listed below: • GMII: When high, indicates that valid data is being transmitted on the phy_txd bus. Synchronous to: clk_tx_o Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 855 The data bus is sampled on both rising and falling edges of the receive clock (phy_clk_rx_i). The validity of the data is qualified with phy_rxdv_i. Synchronous to: phy_ clk_rx_i (both rising and falling edges) Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 856 MDIO signal data out. This signal is driven synchronously with the gmii_mdc_o clock. gmii_mdo_o_e MDIO signal output enable. This signal is driven synchronously with the gmii_mdc_o clock. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 857: Phy Management Interface
The EMAC supports IEEE 1588 operation in all modes with a resolution of one µs. It can be used by the ® ™ Cortex -A9 microprocessor unit (MPU) subsystem to maintain synchronization between the time counters internal to the two MACs. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 858: Functional Description Of The Emac
There are two host interfaces in the EMAC: a slave and a master. The master is connected to the L3 master peripheral switch interface in the L3 interconnect block. Slave The EMAC CSR set access is provided by a slave interface. The slave is connected to the level 4 (L4) bus. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 859: External Phy
C interface The MDIO interface is built into the EMAC while the I C interface uses separate I C peripherals residing on the HPS. The interfaces are multiplexed externally to the EMAC. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 860: Transmit And Receive Data Fifo Buffers
† Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 861 The IEEE 1588 interface to the FPGA allows the FPGA to provide a source for the emac_ptp_ref_clk input as well to allow it to monitor the pulse per second output from each EMAC controller. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 862 Reference Timing Source To get a snapshot of the time, the EMAC takes the reference clock input and uses it to generate the reference † time (64-bit) internally and capture timestamps. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 863 The System Time Update logic requires a 50 MHz clock frequency to achieve 20-ns accuracy. The frequency division ratio (FreqDivisionRatio) is the ratio of the reference clock frequency to the required clock frequency. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 864 SlaveClockCount = SlaveClockTime – † SlaveClockTime • The difference between master and slave clock counts for current sync cycle, ClockDiffCount is given † ClockDiffCount = MasterClockCount – † SlaveClockCount Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 865 This delay is four clock cycles of the PHY interface and three clock cycles of PTP clocks. If the delay between two timestamp captures is less than this delay, the MAC does not take a timestamp snapshot for the second frame. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 866: Ieee 1588-2008 Advanced Timestamps
For details about jam patterns, refer to the IEEE Std 802.3 2008 Part 3: Carrier sense multiple access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, available on the IEEE Standards Association website, (http://standards.ieee.org). Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 867 • Enable the node to be a master or slave and select the timestamp type. This controls the type of messages † for which timestamps are taken. The DMA returns the timestamp to the software inside the corresponding transmit or receive descriptor. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 868: Ieee 802.3Az Energy Efficient Ethernet
Because the most widespread use of Ethernet is to encapsulate TCP and UDP over IP datagrams, the EMAC has a Checksum Offload Engine (COE) to support checksum Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 869: Frame Filtering
Broadcast Address Filter The filter does not filter any broadcast frames in the default mode. However, if the MAC is programmed to † reject all broadcast frames, the filter drops any broadcast frame. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 870 Using the CSR set, you can define up to four filters, identified as filter 0 through filter 3. When multiple Layer 3 and Layer 4 filters are enabled, any filter match is considered as a match. If more than one filter Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 871: Clocks And Resets
Name Functional Usage Notes rst_clk_tx_n_o Transmit clock reset output Used to reset external PHY transmit clock domain logic rst_clk_rx_n_o Receive clock reset output Used to reset external PHY receive clock domain logic Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 872: Interrupts
Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to the next frame buffer when end-of-frame is detected. Data chaining can † be enabled or disabled. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 873 Related Information • Descriptors on page 17-36 Detailed bit map of the descriptor structure • Ethernet MAC Address Map and Register Definitions on page 17-58 Information about Control and Status registers Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 874 However, the DMA always initiates transfers with address aligned to the bus width with dummy data for the byte lanes not required. This typically happens during the transfer of the beginning or end of an Ethernet Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 875 The transmit DMA engine in default mode proceeds as follows: 1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after setting † up the corresponding data buffer(s) with Ethernet frame data. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 876 9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to step 3) when it † receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 877 Status descriptor of the first [if Bit 2 (OSF) in Register 6 (Operation Mode Register) is set]. As the transmit process finishes transferring the first frame, it immediately polls the transmit descriptor list for the second Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 878 Transmit Poll demand (Register 1 (Transmit Poll Demand Register). Note: As the DMA fetches the next descriptor in advance before closing the current descriptor, the descriptor chain should have more than two different descriptors for † correct and proper operation. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 879 (excluding preamble), including the CRC bytes. † Frames can be data-chained and can span several buffers. Frames must be delimited by the First Descriptor (TDES1[29]) and the Last Descriptor (TDES1[30]), respectively. † Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 880 (EOF is not yet transferred), the DMA sets the Descriptor Error bit in the RDES0 (unless flushing is disabled in Bit 24 of Register 6 (Operation Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 881 10. The receive DMA exits the Suspend state when a Receive Poll demand is given or the start of next frame is available from the MTL’s receive FIFO buffer. The engine proceeds to step 2 and refetches the next † descriptor. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 882 (for example, because the receive FIFO buffer was full before the timestamp could be written to it), the DMA writes all-ones to RDES2 and RDES3. Otherwise (that is, if timestamping † is not enabled), the RDES2 and RDES3 remain unchanged. Related Information Receive Descriptor Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 883 There are two groups of interrupts, Normal and Abnormal, as described in Register 5 (Status Register). Interrupts are cleared by writing a 1 to the corresponding bit position. When all the enabled interrupts within Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 884 Fatal Bus Error bit in the Register 5 (Status Register). The DMA controller can resume operation only after soft resetting or hard resetting the EMAC and reinitializing the DMA. (43) Signals NIS and AIS are registered. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 885: Descriptor Overview
• When descriptor is selected without Timestamp or Receive IPC Full Checksum Offload Engine (Type 2) feature, the descriptor size is always 4 DWORDs (DES0-DES3). Therefore, the software can use descriptors with the default size of 16 bytes. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 886 ] 0 : ] 0 : ] 0 : The DMA always reads or fetches four DWORDS of the descriptor from system memory to obtain the buffer † and control information. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 887 When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This † is valid only when the first segment (TDES0[28]) is set. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 888 Furthermore, the Ethernet Length/Type field value for an IPv4 or IPv6 frame must match the IPheader version received with the packet. For IPv4 frames, an error status is † also indicated if the Header Length field has a value less than 0x5. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 889 This is valid only for the frames transmitted without collision when the MAC † operates in the half-duplex mode. NC: No Carrier When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted † during transmission. Reserved Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 890 These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH † (TDES0[20]). Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 891 Register 0 (Bus Mode Register) so that the DMA operates with extended descriptor size. When this control † bit is reset, the RDES0[0] is always cleared and the RDES4-RDES7 descriptor space is not valid. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 892 AFM: Destination Address Filter Fail † When set, this bit indicates a frame that failed in the DA Filter in the MAC. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 893 Note: This bit is set only when the DMA transfers a partial frame to the application. This happens only when the RX FIFO buffer is operating in the threshold mode. In the store- † and-forward mode, all partial frames are dropped completely in RX FIFO buffer. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 894 Watchdog Timeout. RE: Receive Error When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_ i is asserted during frame reception. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 895 (RDES3) is not aligned to bus width. If the buffer size is not an appropriate multiple of 4, the resulting behavior is undefined. This field is not valid if RDES1[14] is set. For more information about calculating buffer sizes, refer to Buffer Size Calculations. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 896 The DMA ignores RDES2[1:0] if the address pointer is to a buffer where the middle or last part of the frame is stored. For more information about buffer address alignment, refer to Host Data Buffer Alignment. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 897 • 11: Filter 3 This field is valid only when Bit 24 or Bit 25 is set high. When more than one filter matches, † these bits give only the lowest filter number. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 898 PTP message is sent over UDP-IPv4 or UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and 7. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 899 EMAC does not match the received checksum bytes, or the IP datagram version is not consistent with the Ethernet Type value. This bit is valid when either Bit 7 or Bit 6 is set. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 900 This field is updated by DMA only for the last descriptor of the receive frame which is indicated by Last Descriptor status bit (RDES0[8]) in RDES0. Related Information Receive Descriptor Field 0 (RDES0) on page 17-43 Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 901: Initializing Dma
(Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor † List Address Register) respectively). 9. Program the following fields to initialize the mode of operation in Register 6 (Operation Mode Register): Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 902: Initializing Mac
• Hash or Perfect Filter † • Unicast, multicast, broadcast, and control frames filter settings † 6. Program the following fields for proper flow control in Register 6 (Flow Control Register): † Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 903: Performing Normal Receive And Transmit Operation
(Register 20 (Current Host Transmit Buffer Address Register) and Register 21 (Current Host Receive Buffer Address Register). † Stopping and Starting Transmission Perform the following steps to pause the transmission for some time: † Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 904: Programming Guidelines For Energy Efficient Ethernet
Gating Off the CSR Clock in the LPI Mode † You can gate off the CSR clock to save the power when the MAC is in the Low-Power Idle (LPI) mode. Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 905: Programming Guidelines For Flexible Pulse-Per-Second (Pps) Output
Once the PPSCMD is executed (PPSCMD bits = 0), you can cancel the pulse generation by giving the Cancel Start Command (PPSCMD=0011) before the programmed start time elapses. You can also program the behavior of the next pulse in advance. To program the next pulse: † Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 906 2. Program a target time value in the Target Time registers (register 455 and 456). This instructs the MAC to generate an interrupt when the target time elapses. If Bits [6:5], TRGTMODSEL, are changed (for Ethernet Media Access Controller Altera Corporation Send Feedback...
Page 907: Ethernet Mac Address Map And Register Definitions
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 • Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 17-21: Document Revision History Date Version Changes December 2013 2013.12.30...
Page 908: Usb 2.0 Otg Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 909: Features Of The Usb Otg Controller
• Supports up to 16 bidirectional endpoints, including control endpoint 0 Note: Only seven periodic device IN endpoints are supported. • Supports a generic root hub • Performs transaction scheduling in hardware USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 910: Supported Phys
• Open Host Controller Interface (OHCI) • Universal Host Controller Interface (UHCI) Supported PHYs Table 18-1: Supported PHYs that are compatible with the USB OTG Manufacturer Part Number TUSB1210 ISP1504 Cypress CY7C68003 SMSC USB3300 USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 911: Usb Otg Controller Block Diagram And System Integration
• Reset input from the reset manager to the USB OTG controller • Interrupt line from the USB OTG controller to the microprocessor unit (MPU) global interrupt controller (GIC). Related Information System Manager Details available in the System Manager chapter. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 912: Functional Description Of The Usb Otg Controller
SPRAM. Slave Interface CSR Unit The slave interface can read from and write to all the CSRs in the USB OTG controllers. All register accesses are 32 bits. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 913 GIC when an ECC error is detected. The MAC module implements the following functionality: • USB transaction support • Host protocol support • Device protocol support • OTG protocol support • Link power management (LPM) functions USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 914 In host mode, the MAC performs the following functions: • Detects connect, disconnect, and remote wakeup events on the USB link • Initiates reset • Initiates speed enumeration processes • Generates Start of Frame (SOF) packets. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 915: Ulpi Phy Interface
The ULPI PHY interface is synchronous to the ulpi_clk signal coming from the PHY. Port Name Bit Width Direction Description Input ULPI Clock ulpi_clk Receives the 60-MHz clock supplied by the high-speed ULPI PHY. All signals are synchronous to the positive edge of the clock. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 916: Clocks
However, if the pin multiplexers are not programmed, the PHY does not see the ulpi_stp signal. As a result, the ulpi_clk clock signal does not arrive at the USB OTG controller. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 917: Interrupts
Host periodic TX FIFO buffer is empty (can be further programmed to Host mode indicate half-empty). Host channels interrupt received. Host mode Incomplete periodic transfer is pending at the end of the microframe. Host mode Host port status interrupt received. Host mode USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 918 OTG interrupts A-Device timeout while waiting for B-Device connection. OTG interrupts Host negotiation is complete. OTG interrupts Session request is complete. OTG interrupts Session end is detected in device mode. OTG interrupts USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 919: Usb Otg Controller Programming Model
6. The USB OTG controller generates an interrupt. The Port Enable Disable Change (prtenchng) and Port Speed (prtspd) bits, in hprt, are set to reflect the enumerated speed of the device that attached. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 920 The USB OTG controller ensures that enough transmit and receive buffers are allocated when the downstream transactions are completed or when accumulated data is ready to be sent upstream. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 921: Device Operation
When an IN token is received on an endpoint when the associated transmit FIFO buffer does not contain sufficient data, the controller performs the following steps: 1. Generates an interrupt 2. Returns a NAK handshake to the USB host USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 922: Usb Otg Controller Address Map And Register Definitions
The base addresses of all modules are listed in the Introduction to the Hard Processor System chapter. • hps.html For more information, refer to the hps.html chapter of the Cyclone V handbook. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 923: Document Revision History
• Described software operation in host and device modes. • Simplified features list. • Simplified hardware descrip- tion. June 2012 Added information about ECCs. January 2012 Initial release. USB 2.0 OTG Controller Altera Corporation Send Feedback...
Page 924: Spi Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 925: Spi Block Diagram
This chapter describes the functional operation of the SPI controller. † The host processor accesses data, control, and status information about the SPI controller through the system bus interface. The SPI also interfaces with the DMA Controller. † SPI Controller Altera Corporation Send Feedback...
Page 926: Spi Controller Overview
† Figure 19-2: Hardware/Software Slave Selection Data Bus Data Bus Master Slave Master Slave ss_0 ss_1 Slave Slave ss = Slave Select Line SPI Controller Altera Corporation Send Feedback...
Page 927 The minimum frequency of l4_main_clk depends on the operation of the slave peripheral. If the slave device is receive only, the minimum frequency of l4_main_clk is six times the maximum expected frequency of the bit-rate clock from the master device (sclk_in). The sclk_in signal is double SPI Controller Altera Corporation Send Feedback...
Page 928 The SPI controller supports combined interrupt requests, which can be masked. The combined interrupt request is the ORed result of all other SPI interrupts after masking. All SPI interrupts have active-high polarity level. The SPI interrupts are described as follows: † SPI Controller Altera Corporation Send Feedback...
Page 929: Transfer Modes
When TMOD = 2, the transmit data are invalid. In the case of the SPI slave, the transmit FIFO buffer is never popped in Receive Only mode. The txd output remains at a constant logic level during the SPI Controller Altera Corporation Send Feedback...
Page 930: Spi Master
Round trip routing delays on the sclk_out signal from the master and the rxd signal from the slave can mean that the timing of the rxd signal, as seen by the master, has moved away from the normal sampling SPI Controller Altera Corporation Send Feedback...
Page 931 FIFO buffer is empty. For continuous data transfers, you must ensure that the transmit FIFO buffer does not become empty before all the data SPI Controller Altera Corporation Send Feedback...
Page 932 If the transfer is nonsequential (MWMOD = 0), it is terminated when the transmit FIFO buffer is empty after shifting in the data frame from the slave. When the transfer is sequential (MWMOD = 1), it is terminated SPI Controller Altera Corporation Send Feedback...
Page 933: Spi Slave
If the master transmits to all serial slaves, a control bit (SLV_OE) in the SPI control register 0 (CTRLR0) can be programmed to inform the slave if it should respond with data from its txd line. † SPI Controller Altera Corporation Send Feedback...
Page 934 FIFO buffer is nearly full. When a DMA Controller is used, the DMA receive data level register (DMARDLR) can be used to early request the DMA controller, indicating that the receive FIFO buffer is nearly full. † Related Information • Motorola SPI Protocol on page 19-12 SPI Controller Altera Corporation Send Feedback...
Page 935: Partner Connection Interfaces
• txd transmit data line for the SPI master or slave † • rxd receive data line for the SPI master or slave † Figure 19-6: SPI Serial Format sclk_out/in 0 4 - 16 bits ss_0_n/ss_in_n ss_oe_n SPI Controller Altera Corporation Send Feedback...
Page 936 Continuous data frames are transferred in the same way as single data frames. The frame indicator is asserted for one clock period during the same cycle as the LSB from the current transfer, indicating that another data frame follows. † SPI Controller Altera Corporation Send Feedback...
Page 937 The Microwire handshaking interface can also be enabled for SPI master write operations to external serial- slave devices. To enable the handshaking interface, you must write 1 into the MHS bit field (bit 2) on the SPI Controller Altera Corporation Send Feedback...
Page 938 Figure 19-9: Single SPI Serial Master Microwire Serial Transfer (MDD=0) sclk_out Control Word 4 - 16 Bits ssi_oe_n Figure 19-10: Single SPI Slave Microwire Serial Transfer (MDD=1) sclk_out Data Word Control Word ss_in_0 ssi_oe_n SPI Controller Altera Corporation Send Feedback...
Page 939: Dma Controller Interface
FIFO buffer onto the slave readback data bus. The FIFO buffers on the SPI controller are not addressable Clocks and Resets The SPI controller uses the clock and reset signals. SPI Controller Altera Corporation Send Feedback...
Page 940: Spi Programming Model
This section describes the programming model for the SPI controller based on the following master and slave transfers: • Master SPI and SSP Serial Transfers • Master Microwire Serial Transfers • Slave SPI and SSP Serial Transfers • Slave Microwire Serial Transfers • Software Control for Slave Selection SPI Controller Altera Corporation Send Feedback...
Page 941: Master Spi And Ssp Serial Transfers
1. If the SPI master is enabled, disable it by writing 0 to the SSI Enable register (SSIENR). 2. Set up the SPI master control registers for the transfer; you can set these transfers in any order. SPI Controller Altera Corporation Send Feedback...
Page 942 5. Poll the BUSY status to wait for the transfer to complete. If a transmit FIFO empty interrupt request is made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read the receive FIFO buffer (read DR). SPI Controller Altera Corporation Send Feedback...
Page 943: Master Microwire Serial Transfers
To complete a Microwire serial transfer from the SPI master, follow these steps: 1. If the SPI master is enabled, disable it by writing 0 to SSIENR. 2. Set up the SPI control registers for the transfer. You can set these registers in any order. SPI Controller Altera Corporation Send Feedback...
Page 944 5. Poll the BUSY status to wait for the transfer to complete. If a transmit FIFO empty interrupt request is made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read the receive FIFO buffer (read DR). SPI Controller Altera Corporation Send Feedback...
Page 945: Slave Spi And Ssp Serial Transfers
If the transmit FIFO makes the request and all data has not been sent, write data to the transmit FIFO. If the receive FIFO makes the request, read data from the receive FIFO. Busy? TMOD = 01 Read Rx FIFO SPI Controller Altera Corporation Send Feedback...
Page 946: Slave Microwire Serial Transfers
6. Write IMR register to set interrupt masks. 7. Write SER register bit[0] to logic '1' to select slave 1 in this example. 8. Write SSIENR register bit[0] to logic '1' to enable SPI master. SPI Controller Altera Corporation Send Feedback...
Page 947: Dma Controller Operation
For details about the DMA burst length microcode setup, refer to the DMA Controller chapter. Transmit Watermark Level Consider the example where the assumption is made: † DMA burst length = FIFO_DEPTH - DMATDLR SPI Controller Altera Corporation Send Feedback...
Page 948 Transmit FIFO FIFO_DEPTH - DMATDLR = 64 Watermark Level Data In Controller Full DMATDLR = 192 Data Out Number of burst transactions in block: † Block transaction size/DMA burst length = 960/64 = 15 † SPI Controller Altera Corporation Send Feedback...
Page 949 SSP Serial Format continuous Transfer figure. It is a trade off between the number of DMA burst transactions required per block versus the probability of an overflow occurring. † SPI Controller Altera Corporation Send Feedback...
Page 950: Spi Controller Address Map And Register Definitions
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter.
Page 951: Document Revision History
Table 19-3: Document Revision History Date Version Changes December 2013 2013.12.30 Minor formatting updates November 2012 Minor updates. May 2012 Added programming model, address map and register definitions, clocks, and reset sections. January 2012 Initial release. SPI Controller Altera Corporation Send Feedback...
Page 952: I 2 C Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 953: I 2 C Controller Block Diagram And System Integration
• Rx shift – Receives data into the design and extracts it in byte format. † • Tx shift – Presents data supplied by CPU for transfer on the I C bus. † • Control logic responsible for implementing the I C protocol. I2C Controller Altera Corporation Send Feedback...
Page 954: Functional Description Of The I C Controller
(NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. † I2C Controller Altera Corporation Send Feedback...
Page 955: Protocol Details
When the bus is idle, both the SCL and SDA signals are pulled high through pull-up resistors on the bus. When the master wants to start a transmission on the bus, the master issues a START condition. This is I2C Controller Altera Corporation Send Feedback...
Page 956 (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0) is the R/W bit. The second byte transferred sets bits 7:0 of the slave address. † I2C Controller Altera Corporation Send Feedback...
Page 957 All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the master sends the address and R/W bit or the master transmits a byte of data to the slave, the slave- I2C Controller Altera Corporation Send Feedback...
Page 958 0 (Write) 11110xxx 1 (Read) From Master to Slave S: Start Condition R: Restart Condition From Slave to Master P: Stop Condition R/W: Read/Write Pulse A: Acknowledge (SDA Low) A: No Acknowledge (SDA High) I2C Controller Altera Corporation Send Feedback...
Page 959: Multiple Master Arbitration
† Upon detecting that it has lost arbitration to another master, the I C controller stops generating SCL. † The following figure illustrates the timing of two masters arbitrating on the bus. I2C Controller Altera Corporation Send Feedback...
Page 960 HIGH wait state. Therefore, a synchronized SCL clock is generated, which is illustrated in the following figure. Optionally, slaves may hold the SCL line low to slow down the timing on the I C bus. † I2C Controller Altera Corporation Send Feedback...
Page 961: Clock Frequency Configuration
† Consequently, the minimum SCL low time of which the I C controller is capable is nine (9) l4_sp_clk periods (8+1), while the minimum SCL high time is thirteen (13) l4_sp_clk periods (6+1+3+3). † I2C Controller Altera Corporation Send Feedback...
Page 962: Sda Hold Time
Board delays on the SCL and SDA signals can mean that the hold time requirement is met at the I master, but not at the I C slave (or vice-versa). As each application encounters differing board delays, the I2C Controller Altera Corporation Send Feedback...
Page 963: Dma Controller Interface
The pins must be connected to a pull-up resistors and the I C bus capacitance cannot exceed 400 pF. Table 20-3: I C Controller Interface Pins Pin Name Signal Width Direction Description 1 bit Bidirectional Serial clock 1 bit Bidirectional Serial data I2C Controller Altera Corporation Send Feedback...
Page 964: I 2 C Controller Programming Model
For more information on configuring open drain I/O buffer to connect I C signals to external I/O pins, please refer to Altera I/O Buffer (ALTIOBUF) Megafunction User Guide C Controller Programming Model This section describes the programming model for the I C controllers based on the two master and slave operation modes.
Page 965 5. Software writes to the DAT bits of the IC_DATA_CMD register with the data to be written and writes a 0 in bit 8.† 6. Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6, respectively) of the IC_RAW_INTR_STAT register before proceeding. † I2C Controller Altera Corporation Send Feedback...
Page 966 If the RD_REQ interrupt is masked, due to bit 5 (M_RD_REQ) of the IC_INTR_STAT register being set to 0, then it is recommended that the CPU does periodic reads of the IC_RAW_INTR_STAT register. Reads I2C Controller Altera Corporation Send Feedback...
Page 967: Master Mode Operation
5. Now write the transfer direction and data to be sent to the IC_DATA_CMD register. If the IC_DATA_CMD register is written before the I C controller is enabled, the data and commands are lost as the buffers are kept cleared when the I C controller is not enabled. † I2C Controller Altera Corporation Send Feedback...
Page 968: Disabling The I2C Controller
Writing a 1 to the RDMAE bit field of the IC_DMA_CR register enables the I controller receive handshaking interface.† The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the I C controller is 64 entries. I2C Controller Altera Corporation Send Feedback...
Page 969 • Block transaction size = 240: † Figure 20-11: Transmit FIFO Watermark Level = 16 Transmit FIFO Buffer FIFO_DEPTH = 64 FIFO_DEPTH - IC_DMA_TDLR = 48 Empty Data In Controller Transmit FIFO IC_DMA_TDLR = 16 Watermark Level Full Data Out I2C Controller Altera Corporation Send Feedback...
Page 970 FIFO to service the destination burst request. Therefore, the following equation must be adhered to in order to avoid overflow: † DMA burst length <= FIFO_DEPTH - IC_DMA_TDLR I2C Controller Altera Corporation Send Feedback...
Page 971 The receive FIFO will not be empty at the end of the source burst transaction if the I C controller has successfully received one data item or more on the I C serial receive line during the burst. † I2C Controller Altera Corporation Send Feedback...
Page 972: I 2 C Controller Address Map And Register Definitions
1-1 For more information, refer to Introduction to the Hard Processor System . • hps.html For more information, refer to the hps.html chapter of the Cyclone V handbook. Document Revision History Table 20-5: Document Revision History Date Version...
Page 973 20-22 Document Revision History 2013.12.30 Date Version Changes May 2012 Added programming model, address map and register definitions, clocks, reset, and interface pins sections. January 2012 Initial release. I2C Controller Altera Corporation Send Feedback...
Page 974: Uart Controller
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 975: Uart Controller Block Diagram And System Integration
Converts the serial data character (as specified by the control register) received in the UART format to parallel form. Parity error detection, framing error detection and line break detection is carried out in this block. † UART Controller Altera Corporation Send Feedback...
Page 976: Functional Description Of The Uart Controller
FIFO buffer. † Automatic Flow Control The UART includes 16750-compatible request-to-send (RTS) and clear-to-send (CTS) serial data automatic flow control mode. You enable automatic flow control with the modem control register (MCR.AFCE). † UART Controller Altera Corporation Send Feedback...
Page 977 When using the FIFO buffer full status, software can poll this before each write to the transmit FIFO buffer. When the cts_n input becomes active (low) again, transmission resumes. If the FIFO buffers are disabled UART Controller Altera Corporation Send Feedback...
Page 978: Clocks
THRE interrupt mode with the interrupt enable register (IER_DLH.PTIME). When the THRE mode is enabled, THRE interrupts and the dma_tx_req signal are active at and below a programmed transmit FIFO buffer empty threshold level, as shown in the flowchart. † UART Controller Altera Corporation Send Feedback...
Page 979 You can increase system efficiency when this mode is enabled in combination with automatic flow control. When not selected or disabled, THRE interrupts and LSR.THRE function normally, reflecting an empty THR or FIFO buffer. UART Controller Altera Corporation Send Feedback...
Page 980: Uart Controller Programming Model
(TET) field in the FIFO Control Register (IIR_FCR), also known as the watermark level. The DMA controller responds by writing a burst of data to the transmit FIFO buffer, of length specified as DMA burst length. † UART Controller Altera Corporation Send Feedback...
Page 981 FIFO. This occurs because the DMA has not had time to service the DMA request before the FIFO becomes empty. IIR_FCR.TET = 3 IIR_FCR.TET = 3 decodes to a watermark level of 64. UART Controller Altera Corporation Send Feedback...
Page 982 The transmit FIFO will not be full at the end of a DMA burst transfer if the UART controller has successfully transmitted one data item or more on the UART serial transmit line during the transfer. † UART Controller Altera Corporation Send Feedback...
Page 983: Uart Controller Address Map And Register Definitions
IIR_FCR.RT Data In UART Controller Address Map and Register Definitions The address map and register definitions reside in the hps.html file that accompanies this handbook volume. Click the link to open the file. UART Controller Altera Corporation Send Feedback...
Page 984: Document Revision History
Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 For more information, refer to the Introduction to the Hard Processor System chapter of the Cyclone V Device Handbook, Volume 3. • hps.html For more information, refer to hps.html.
Page 985: General-Purpose I/O Interface
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 986: Functional Description Of The Gpio Interface
22-2 Functional Description of the GPIO Interface 2013.12.30 Figure 22-1: Cyclone V SoC GPIO GPIO Interface gpio_rst_n[n] Reset Manager Cortex A9 Subsystem gpio_intr_in Interrupt & Core Generic Interrupt Control Controller Clock Manager Register Block GPIO[28:0] GPIO 0 GPIO[57:29] GPIO 1...
Page 987: Pin Directions
• gpio1 • gpio2 To then view the register and field descriptions, scroll to and click the register names. The register addresses are offsets relative to the base address of each module instance. General-Purpose I/O Interface Altera Corporation Send Feedback...
Page 988: Document Revision History
22-4 Document Revision History 2013.12.30 Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 For more information, refer to Introduction to the Hard Processor System . • hps.html For more information, refer to this hps.html reference.
Page 989: Timer Introduction
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 990: Functional Description Of The Timer
This table shows the clock signals and connections associated with the timers. Timer System Clock Notes OSC1 timer 0 osc1_clk OSC1 timer 1 SP timer 0 Timer must be disabled if clock l4_sp_clk frequency changes SP timer 1 Timer Introduction Altera Corporation Send Feedback...
Page 991: Resets
• Set the interrupt mask as either masked or not masked by writing a 1 or 0, respectively, to the timer1_interrupt_mask bit of the timer1controlreg register. † 2. Load the timer counter value into the timer1loadcount register. † Timer Introduction Altera Corporation Send Feedback...
Page 992: Enabling The Timer
1. To check the interrupt status, read the timer1intstat register. † Masking the Interrupt The timer interrupt can be masked using the timer1controlreg register. 1. To mask an interrupt, write a 1 to the timer1_interrupt_mask bit of the timer1controlreg register. † Timer Introduction Altera Corporation Send Feedback...
Page 993: Timer Address Map And Register Definitions
1-1 For more information, refer to the Introduction to the Hard Processor System chapter. • hps.html For more information, refer to this hps.html chapter of the Cyclone V Device Handbook. Document Revision History Table 23-2: Document Revision History Date...
Page 994: Watchdog Timer
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 995: Watchdog Timer Block Diagram And System Integration
In the latter case, the generated interrupt is passed to the generic interrupt controller (GIC) in the Watchdog Timer Altera Corporation Send Feedback...
Page 996: Watchdog Timer Pause Mode
Watchdog timers are reset by a cold or warm reset from the reset manager, and are disabled when exiting reset. † Related Information Reset Manager on page 3-1 For more information, refer to the Reset Manager chapter. Watchdog Timer Altera Corporation Send Feedback...
Page 997: Watchdog Timer Programming Model
Features of the System Manager on page 14-1 For more information, refer to the System Manager chapter of the Cyclone V Device Handbook, Volume 3. Disabling and Stopping a Watchdog Timer The watchdog timers are disabled and stopped only by resetting them from the reset manager.
Page 998: Watchdog Timer State Machine
Assert Interrupt and Load Counter with Restart Timeout Value. An interrupt to the processor is generated, and the watchdog counter is reloaded with the restart timeout value. The state then changes to the second Decrement Counter state, and the counter resumes decrementing. If software Watchdog Timer Altera Corporation Send Feedback...
Page 999: Watchdog Timer Address Map And Register Definitions
To then view the register and field descriptions, scroll to and click the register names. The register addresses are offsets relative to the base address of each module instance. Related Information • Introduction to Cyclone V Hard Processor System (HPS) on page 1-1 For more information, refer to the Introduction to the Hard Processor System. •...
Page 1000: Can Controller Introduction
Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Altera Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

Embedded Memory Blocks in Cyclone V Devices

Variable Precision DSP Blocks in Cyclone V Devices

Clock Networks and Plls in Cyclone V Devices

I/O Features in Cyclone V Devices

External Memory Interfaces in Cyclone V Devices

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

SEU Mitigation for Cyclone V Devices

JTAG Boundary-Scan Testing in Cyclone V Devices

Power Management in Cyclone V Devices

Volume 2: Transceivers

Transceiver Architecture in Cyclone V Devices

Transceiver Clocking in Cyclone V Devices

Transceiver Reset Control in Cyclone V Devices

Transceiver Protocol Configurations in Cyclone V Devices

Transceiver Loopback Support

Dynamic Reconfiguration in Cyclone V Devices

Quick Links

Chapters

Related Manuals for Altera Cyclone V

Summary of Contents for Altera Cyclone V