Functional Description Of The Emac - Altera cyclone V Technical Reference

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Functional Description of the EMAC

Functional Description of the EMAC
Figure 17-3: EMAC High-Level Block Diagram with Interfaces
Master
Interface
Slave
Interface
There are two host interfaces to the Ethernet MAC. The management host interface, a 32-bit slave
interface, provides access to the CSR set. The data interface is a 32-bit master interface, and it controls data
transfer between the direct memory access (DMA) controller channels and the rest of the HPS system
through the system interconnect.
The built-in DMA controller is optimized for data transfer between the MAC controller and system
memory. The DMA controller has independent transmit and receive engines and a CSR set. The transmit
engine transfers data from system memory to the device port, while the receive engine transfers data from
the device port to the system memory. The controller uses descriptors to efficiently move data from source
to destination with minimal host intervention.
The EMAC also contains FIFO buffer memory to buffer and regulate the Ethernet frames between the
application system memory and the EMAC module. Each EMAC module has one 4 KB TX FIFO and one
4 KB RX FIFO. On transmit, the Ethernet frames write into the transmit FIFO buffer, and eventually
trigger the EMAC to perform the transfer. Received Ethernet frames are stored in the receive FIFO buffer
and the FIFO buffer fill level is communicated to the DMA controller. The DMA controller then initiates
the configured burst transfers. Receive and transmit transfer statuses are read by the EMAC and
transferred to the DMA.
Altera Corporation
EMAC
TX FIFO Buffer
(DPRAM)
DMA
TX FIFO Buffer
Controller
Controller
DMA Operation Mode
CSRs Register
RX FIFO Buffer
(DPRAM)
RX FIFO Buffer
Controller
MAC
2016.10.28
PHY
Interface
Ethernet Media Access Controller
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