Altera cyclone V Technical Reference page 245

cv_5v4
2016.10.28
ctrl
Registers used by the DMA Controller. All fields are reset by a cold or warm reset. These register bits
should be updated during system initialization prior to removing the DMA controller from reset. They
may not be changed dynamically during DMA operation.
Module Instance
sysmgr
Offset:
0x70
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
ctrl Fields
Bit
12:5
irqnonsecure
4
mgrnonsecure
System Manager
Send Feedback
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Specifies the security state of an event-interrupt
resource. If bit index [x] is 0, the DMAC assigns
event<x> or irq[x] to the Secure state. If bit index [x]
is 1, the DMAC assigns event<x> or irq[x] to the
Non-secure state.
Specifies the security state of the DMA manager
thread. 0 = assigns DMA manager to the Secure state.
1 = assigns DMA manager to the Non-secure state.
Sampled by the DMA controller when it exits from
reset.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
irqnonsecure
RW 0x0
Description
Register Address
0xFFD08070
21 20 19 18
5 4 3 2
mgrno chans chans
nsecu el_3 el_2
re
RW RW
RW 0x0 0x0
0x0
Access
5-51
ctrl
17 16
1 0
chans chansel_
el_1 0
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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