Altera cyclone V Technical Reference page 939

13-118
dma_intr
31 30
15 14
dma_enable Fields
Bit
0
flag
dma_intr
DMA interrupt register
Module Instance
nandregs
Offset:
0x720
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dma_intr Fields
Bit
0
target_error
Altera Corporation
29 28 27 26
13 12 11 10
Name
Enables data DMA operation in the controller 1 -
Enable DMA 0 - Disable DMA
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Controller initiator interface received an ERROR
target response for a transaction.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB80720
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
17 16
1 0
target_
error
RW 0x0
Reset
RW 0x0
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