Slave Interface And Status Register; Functional Description Of The Reset Manager - Altera cyclone V Technical Reference

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Slave Interface and Status Register

HPS Peripheral
UART
SPI Master
SPI Slave
SD/MMC
CAN
GPIO
DMA
SDRAM
DMA Peripheral Interfaces
HPS-to-FPGA Bridge
FPGA-to-HPS Bridge
Lightweight HPS-to-FPGA Bridge
Slave Interface and Status Register
The reset manager slave interface is used to control and monitor the reset states.
The status register (
contains a bit for each monitored reset request. The
occurred. Software is responsible for clearing the bits.
During the boot process, the Boot ROM copies the
After booting, you can read the value of the reset status register at memory address (
more information, refer to the "Shared Memory" section of the Booting and Configuration appendix.
Related Information
Shared Memory

Functional Description of the Reset Manager

The reset manager generates reset signals to modules in the HPS and to the FPGA fabric. The following
actions generate reset signals:
• Software writing a 1 to the
causes the reset controller to perform a reset sequence.
• Software writing to the
control registers.
• Asserting reset request signals triggers the reset controller. All external reset requests cause the reset
controller to perform a reset sequence.
Multiple reset requests can be driven to the reset manager at the same time. Cold reset requests take
priority over warm and debug reset requests. Higher priority reset requests preempt lower priority reset
requests. There is no priority difference among reset requests within the same domain.
Altera Corporation
Reset Register
permodrst
permodrst
permodrst
permodrst
permodrst
permodrst
permodrst
permodrst
per2modrst
brgmodrst
brgmodrst
brgmodrst
) in the reset manager contains the status of the reset requester. The register
stat
on page 30-31
swcoldrstreq
,
mpumodrst permodrst
Module Reset Signal
uart_rst_n[1:0]
spim_rst_n[1:0]
spis_rst_n[1:0]
sdmmc_rst_n
can_rst_n[1:0]
gpio_rst_n[2:0]
dma_rst_n
sdram_rst_n
dma_periph_if_rst_n[7:0]
hps2fpga_bridge_rst_n
fpga2hps_bridge_rst_n
lwhps2fpga_bridge_rst_n
register captures all reset requests that have
stat
register value into memory before clearing it.
stat
or bits in the
swwarmrstreq
, ,
per2modrst brgmodrst
Reset Group
PER
PER
PER
PER
PER
PER
PER
PER
PER2
Bridge
Bridge
Bridge
+ 0x0038). For
r0
register. Writing either bit
ctrl
, or module reset
miscmodrst
Reset Manager
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cv_5v4
2016.10.28