Cortex-A9 Mpu Subsystem Internals - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Cortex-A9 MPU Subsystem Internals

Figure 9-2: Cortex-A9 MPU Subsystem Block Diagram
Cortex-A9 Microprocessor Unit Subsystem
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Cortex-A9 MPU Subsystem
ARM Cortex-A9 MPCore
CPU0
ARM Cortex-A9 Processor
NEON Media SIMD
Processing Engine with FPU
MMU
32 KB
Instruction
Cache
CPU0 Private
Watchdog Timer
Interval Timer
Accelerator Coherency Port
ACP ID Mapper
Debugging Modules
CPU0 Performance Monitor
CPU0 Program Trace
CPU1 (Dual-Core HPS Only)
ARM Cortex-A9 Processor
Processing Engine with FPU
32 KB
32 KB
Data
Instruction
Cache
Cache
CPU0 Private
CPU1 Private
Interval Timer
GIC (Generic Interrupt Controller)
Global Timer
Snoop Control Unit
512 KB L2 Cache
CoreSight Multicore Debug and Trace
Cross Triggering
Event Trace
Cortex-A9 MPU Subsystem Internals
NEON Media SIMD
MMU
32 KB
Data
Cache
CPU1 Private
Watchdog Timer
CPU1 Performance Monitor
CPU1 Program Trace
9-3
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