Altera cyclone V Technical Reference page 221

Hard processor system

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Specifies the sampled value of the HPS BSEL pins. The

value of HPS BSEL pins are sampled upon deassertion

of cold reset.

The clock select field specifies clock information for

booting. The clock select encoding is a function of the

CSEL value. The clock select field is read by the Boot

ROM code on a cold or warm reset when booting

from a flash device to get information about how to

setup the HPS clocking to boot from the specified

clock device. The encoding of the clock select field is

specified by the enum associated with this field. The

HPS CSEL pins value are sampled upon deassertion

of cold reset.

QSPI device clock is osc1_clk divided by 4,

SD/MMC device clock is osc1_clk divided by

4, NAND device operation is osc1_clk

divided by 25

QSPI device clock is osc1_clk divided by 2,

SD/MMC device clock is osc1_clk divided by

1, NAND device operation is osc1_clk

multiplied by 20/25

QSPI device clock is osc1_clk divided by 1,

SD/MMC device clock is osc1_clk divided by

2, NAND device operation is osc1_clk

multiplied by 10/25

QSPI device clock is osc1_clk multiplied by 2,

SD/MMC device clock is osc1_clk divided by

4, NAND device operation is osc1_clk

multiplied by 5/25

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