Altera cyclone V Technical Reference page 1000

14-54
cmd Register Settings for Single-Block and Multiple-Block Write
1. Write the data size in bytes to the
of the block size.
2. Write the block size in bytes to the
†
each.
3. Write the
4. Write data into the FIFO buffer. For best performance, the host software should write data continu‐
ously until the FIFO buffer is full.
5. Write the
Block Write. For SD and MMC cards, use the SD/SDIO WRITE_BLOCK (CMD24) command for a
single-block write and the WRITE_MULTIPLE_BLOCK (CMD25) command for a multiple-block
writes. For SDIO cards, use the IO_RW_EXTENDED command for both single-block and
multiple-block transfers.
After writing to the
command already being processed. When the command is sent to the bus, a Command Done interrupt
is generated.
6. Software must check for data error interrupts; that is, for
register. If required, software can terminate the data transfer early by sending the SD/SDIO STOP
command.
7. Software must check for host timeout conditions in the
• Transmit FIFO buffer data request.
• Data starvation by the host—the controller wrote data to the card faster than the host could supply
the data.
In both cases, the software must write data into the FIFO buffer.
There are two types of transfers: open-ended and fixed length.
• Open-ended transfers—For an open-ended block transfer, the byte count is 0. At the end of the data
transfer, software must send the STOP_TRANSMISSION command (CMD12).
• Fixed-length transfers—The byte count is nonzero. You must already have written the number of
bytes to the
send_auto_stop
bytes, the controller sends the STOP command. Completion of the AUTO_STOP command is
reflected by the Auto Command Done interrupt. A response to the AUTO_STOP command is
written to the
1, software must issue the STOP command just like in the open-ended case.
When the
cmd Register Settings for Single-Block and Multiple-Block Write
Table 14-24: cmd Register Settings for Single-Block and Multiple-Block Write (Default)
Parameter
start_cmd
use_hold_reg
update_clk_regs_only
Altera Corporation
†
register with the data address to which data must be written.
cmdarg
register with the parameters listed in cmd Register Settings for Single-Block and Multiple-
cmd
†
register, the controller starts executing a command if there is no other
cmd
†
†
†
register. The controller issues the STOP command for you if you set the
bytcnt
bit of the
cmd
register. If software does not set the
resp1
bit of the register is set, the data command is complete.
dto rintsts
register. For a multi-block write,
bytcnt
register. The controller sends data in blocks of size
blksiz
†
rintsts
†
register to 1. After completion of a transfer of a given number of
Value
1 This bit resets itself to 0 after the command is committed
(accepted by the BIU).
1 or 0 Choose the value based on speed mode used.
0 Does not need to update clock parameters
bytcnt
†
, , and bits of the
dcrc bds ebe
†
register:
†
†
bit in the
send_auto_stop
†
†
†
Comment
cv_5v4
2016.10.28
must be a multiple
blksiz
rintsts
†
register to
cmd
SD/MMC Controller
Send Feedback