Dma Controller - Altera cyclone V Technical Reference

17-16

DMA Controller

Register 6 (Operation Mode Register). The time at which data is sent from the RX FIFO to the DMA is
dependent on the configuration of the RX FIFO:
• Cut-through (default) mode: When 64 bytes or a full packet of data is received into the FIFO, data is
popped out of the FIFO and sent to the DMA until a complete packet has been transferred. Upon
completion of the end-of-frame transfer, the status word is popped and sent to the DMA.
• Store and forward mode: A frame is read out only after being written completely in the RX FIFO. This
mode is configured by setting the
If the RX FIFO is full before it receives the EOF data from the EMAC, an overflow is declared and the
whole frame (including the status word) is dropped and the overflow counter in the DMA, (Register 8)
Missed Frame and Buffer Overflow Counter Register, is incremented. This outcome is true even if the
Forward Error Frame (
frame has already been transferred, the rest of the frame is dropped and a dummy EOF is written to the
FIFO along with the status word. The status indicates a partial frame because of overflow. In such frames,
the Frame Length field is invalid. If the RX FIFO is configured to operate in the store-and-forward mode
and if the length of the received frame is more than the FIFO size, overflow occurs and all such frames are
dropped.
Note: In store-and-forward mode, only received frames with length 3800 bytes or less prevent overflow
errors and frames from being dropped.
DMA Controller
The DMA has independent transmit and receive engines, and a CSR space. The transmit engine transfers
data from system memory to the device port or MAC transaction layer (MTL), while the receive engine
transfers data from the device port to the system memory. Descriptors are used to efficiently move data
from source to destination with minimal Host CPU intervention. The DMA is designed for packet-
oriented data transfers such as frames in Ethernet. The controller can be programmed to interrupt the
Host CPU for situations such as frame transmit and receive transfer completion as well as error
conditions.
The DMA and the Host driver communicate through two data structures:
• Control and Status registers (CSR)
• Descriptor lists and data buffers
Because the Cyclone V implementation of the Ethernet MAC only supports enhanced descriptors, all
mentions of descriptors in the following text refer to enhanced descriptors.
Descriptor Lists and Data Buffers
The DMA transfers data frames received by the MAC to the receive Buffer in the Host memory, and
transmit data frames from the transmit Buffer in the Host memory. Descriptors that reside in the Host
memory act as pointers to these buffers.
There are two descriptor lists: one for reception and one for transmission. The base address of each list is
written into Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor List
Address Register), respectively. A descriptor list is forward linked (either implicitly or explicitly). The last
descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is
accomplished by setting the second address chained in both receive and transmit descriptors (RDES1[14]
and TDES0[20]). The descriptor lists resides in the Host physical memory address space. Each descriptor
can point to a maximum of two buffers. This enables two buffers to be used, physically addressed, rather
than contiguous buffers in memory.
Altera Corporation
bit of Register 6 (Operation Mode Register).
RSF
) bit of Register 6 (Operation Mode Register) is set. If the start address of such a
FEF
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Ethernet Media Access Controller
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cv_5v4
2016.10.28