Altera cyclone V Technical Reference page 866

cv_5v4
2016.10.28
program_wait_cnt Fields
Bit
15:0
value
erase_wait_cnt
Wait count value for Erase operation
Module Instance
nandregs
Offset:
0x40
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
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Name
Number of clock cycles after issue of program
operation before NAND Flash Controller polls for
status. This values is of relevance for status polling
mode of operation and has been provided to
minimize redundant polling after issuing a command.
After a program command, the first polling will
happen after this many number of cycles have elapsed
and then on polling will happen every int_mon_
cyccnt cycles. The default values is equal to the default
value of int_mon_cyccnt. The controller internally
multiplies the value programmed into this register by
16 to provide a wider range for polling.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x1F4
erase_wait_cnt
Access
Register Address
0xFFB80040
21 20 19 18
5 4 3 2
13-45
Reset
RW 0x1F4
17 16
1 0
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