Altera cyclone V Technical Reference page 82

cv_5v4
2016.10.28
dbgdiv Fields
Bit
3:2
dbgclk
1:0
dbgatclk
tracediv
Contains a field that controls the clock divider for the debug trace clock derived from the Main PLL Only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x6C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Clock Manager
Send Feedback
Name
The dbg_clk is divided down from the dbg_at_clk by
the value specified in this field.
0x1
0x2
The dbg_at_clk is divided down from the C2 output
of the Main PLL by the value specified in this field.
0x0
0x1
0x2
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Value Description
Divide by 2
Divide by 4
Value Description
Divide by 1
Divide by 2
Divide by 4
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
tracediv
Access
Register Address
0xFFD0406C
21 20 19 18
5 4 3 2
2-45
Reset
RW 0x1
RW 0x0
17 16
1 0
traceclk
RW 0x0
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