Altera cyclone V Technical Reference page 994

14-48
cmd Register Settings for Non-Data Transfer Command
response registers (
MSB and bit 0 of
For basic and non-data transfer commands, perform the following steps:
1. Write the
2. Write the
3. Wait for the controller to accept the command. The
accepted.
The following actions occur when the command is loaded into the controller:
• If no previous command is being processed, the controller accepts the command for execution and
resets the
controller loads the new command in the command buffer.
• If the controller is unable to load the new command—that is, a command is already in progress, a
second command is in the buffer, and a third command is attempted—the controller generates a
hardware lock error.
4. Check if there is a hardware lock error.
5. Wait for command execution to complete. After receiving either a response from a card or response
timeout, the controller sets the
for this bit or respond to a generated interrupt (if enabled).
6. Check if the response timeout boot acknowledge received (
either respond to an interrupt raised by these errors or poll the
register. If no response error is received, the response is valid. If required, software can copy the
response from the response registers.
Note: Software cannot modify clock parameters while a command is being executed.
Related Information
cmd Register Settings for Non-Data Transfer Command†
Refer to this table for information about Non-Data Transfer commands.
cmd Register Settings for Non-Data Transfer Command
Table 14-20: Default
Parameter
start_cmd
use_hold_reg
update_clk_regs_only
data_expected
card_number
Altera Corporation
, ,
resp0 resp1 resp2
represents the LSB.
resp0
register with the appropriate command argument parameter.
cmdarg
register with the settings in Register Settings for Non-Data Transfer Command.
cmd
†
bit in the
start_cmd
†
command_done
1
1 or 0
0
0
1
†
†
, and ). For long responses, bit 31 of
resp3
†
start_cmd
register to 0. If a previous command is being processed, the
cmd
†
bit in the
rintsts
†
on page 14-48
†
Value
This bit resets itself to 0 after the command is
committed.
Choose the value based on the speed mode used.
Indicates that the command is not a clock update
command
Indicates that the command is not a data
command
For one card
resp3
†
bit changes to 0 when the command is
†
†
register to 1. Software can either poll
†
), , or bit is set to 1. Software can
bar rcrc re
, , and bits of the
re rcrc bar
†
Comment
cv_5v4
2016.10.28
represents the
†
rintsts
SD/MMC Controller
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