Coresight Debug And Trace Address Map And Register Definitions - Altera cyclone V Technical Reference

10-22
Triggering a Breakpoint on CPU 1
HPS. For example, configure channel 1 to trigger output 4 in csCTI. Then configure trigger input T2 to
channel 1 in FPGA-CTI.
Triggering a Breakpoint on CPU 1
Another soft logic signal in the FPGA fabric connected to trigger input T1 in FPGA-CTI can be
configured to trigger a breakpoint on CPU 1. Trigger output 1 in CTI-1 is wired to the external debug
request (EDBGRQ) signal of CPU-1. For example, configure channel 2 to trigger output 1 in CTI-1. Then
configure trigger input T1 to channel 2 in FPGA-CTI.

CoreSight Debug and Trace Address Map and Register Definitions

The address map and register definitions for CoreSight Debug and Trace consist of the following regions:
System Trace Macrocell (STM) Module Address Map
This address space holds the registers used for Coresight System Trace Macrocell. For detailed information
about the STM module and register descriptions,
CoreSight STM-101.
Debug Access Port (DAP) Module Address Map
This address space is allocated to the Debug Access Port (DAP). For detailed information about the use of
this address space,
MPU Address Map
This address space is allocated to the MPU. For detailed information about the use of this address space,
click here
MPU L2 Cache Controller (L2C-310) Module Address Map
This address space is allocated to the MPU L2 cache controller. For detailed information about the use of
this address space,
Related Information
Introduction to the Hard Processor System
•
The base addresses of all modules are also listed in the Introduction to the Hard Processor System
chapter.
• System Trace Macrocell (STM) Module Address Map
This address space holds the registers used for Coresight System Trace Macrocell. For detailed information
about the STM module and register descriptions,
CoreSight STM-101.
Debug Access Port (DAP) Module Address Map
•
This address space is allocated to the Debug Access Port (DAP). For detailed information about the use of
this address space,
• MPU Address Map
This address space is allocated to the MPU. For detailed information about the use of this address space,
click here
MPU L2 Cache Controller (L2C-310) Module Address Map
•
This address space is allocated to the MPU L2 cache controller. For detailed information about the use of
this address space,
Cyclone V Address Map and Register Definitions
•
Web-based address map and register definitions
Altera Corporation
click here
to access the ARM documentation for the DAP.
on page 10-25
to access the ARM documentation for the Cortex-A9 MPCore.
click here
to access the ARM documentation for the L2C-310.
click here
to access the ARM documentation for the DAP.
on page 10-25
to access the ARM documentation for the Cortex-A9 MPCore.
click here to access the ARM documentation for the L2C-310.
on page 10-23
click here to access the ARM documentation for the
on page 10-23
on page 10-26
on page 1-1
on page 10-23
click here
to access the ARM documentation for the
on page 10-23
on page 10-26
cv_5v4
2016.10.28
CoreSight Debug and Trace
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