Altera cyclone V Technical Reference page 702

9-66
L2 Cache Lockdown Capabilities
cache maintenance operations, if a parity error occurs on tag or data RAM, the error is reported back
through the interrupt lines only. In addition, the L2 Cache cannot refill a line from external memory due
to a parity error.
Related Information
ARM Infocenter
L2 Cache Lockdown Capabilities
The L2 cache has three methods to lock data in the cache RAMs:
• Lockdown by line—Used to lock lines in the cache. This is commonly used for loading critical sections
of software into the cache temporarily.
• Lockdown by way—Allows any or all of the eight cache ways to be locked. This is commonly used for
loading critical data or code into the cache.
• Lockdown by master—Allows cache ways to be dedicated to a single master port. This allows a large
cache to look like smaller caches to multiple master ports. The L2 cache can be mastered by CPU0,
CPU1, or the six ACP masters, for a total of eight possible master ports.
Related Information
ARM Infocenter
For more information about L2 cache lockdown capabilities, refer to "Cache operation" in the Functional
Overview chapter of the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, available
on the ARM Infocenter website.
L2 Cache Event Monitoring
The L2 cache supports the built-in cache event monitoring signals shown in the table below. The L2 cache
can count two of the events at any one time.
Table 9-12: L2 Cache Events
CO
DRHIT
DRREQ
DWHIT
DWREQ
DWTREQ
Altera Corporation
Event Description
Eviction (cast out) of a line from the L2 cache.
Data read hit in the L2 cache.
Data read lookup to the L2 cache. Subsequently
results in a hit or miss.
Data write hit in the L2 cache.
Data write lookup to the L2 cache. Subsequently
results in a hit or miss.
Data write lookup to the L2 cache with
write-through attribute. Subsequently results in a hit
or miss.
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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