Altera cyclone V Technical Reference page 274

5-80
emac1
Bit
4
rxfifoinjd
3
rxfifoinjs
2
txfifoinjd
1
txfifoinjs
0
en
emac1
This register is used to enable ECC on the EMAC1 RAM. ECC errors can be injected into the write path
using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only
reset by a cold reset (ignores warm reset).
Module Instance
sysmgr
Offset:
0x154
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
Changing this bit from zero to one injects a double,
non-correctable error into the EMAC0 RXFIFO
RAM. This only injects one double bit error into the
EMAC0 RXFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the EMAC0 RXFIFO RAM.
This only injects one error into the EMAC0 RXFIFO
RAM.
Changing this bit from zero to one injects a double,
non-correctable error into the EMAC0 TXFIFO
RAM. This only injects one double bit error into the
EMAC0 TXFIFO RAM.
Changing this bit from zero to one injects a single,
correctable error into the EMAC0 TXFIFO RAM.
This only injects one error into the EMAC0 TXFIFO
RAM.
Enable ECC for EMAC0 RAM
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
rxfif rxfif txfif
oderr oserr oderr
RW RW RW
0x0 0x0 0x0
Register Address
0xFFD08154
21 20 19 18
5 4 3 2
txfif rxfif rxfif txfif
oserr oinjd oinjs oinjd
RW RW RW RW
0x0 0x0 0x0 0x0
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
17 16
1 0
txfif en
oinjs
RW 0x0
RW
0x0
System Manager
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