Altera cyclone V Technical Reference page 343

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
MIXED1IO18 Fields
Bit
1:0
sel
MIXED1IO19
This register is used to control the peripherals connected to qspi_ss0 Only reset by a cold reset (ignores
warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for
dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x54C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
System Manager
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select peripheral signals connected qspi_io3. 0 : Pin is
connected to GPIO/LoanIO number 32. 1 : Pin is
connected to Peripheral signal USB1.NXT. 2 : Pin is
connected to Peripheral signal not applicable. 3 : Pin
is connected to Peripheral signal QSPI.IO3.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
MIXED1IO19
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD0854C
21 20 19 18
5 4 3 2
5-149
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
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