Altera cyclone V Technical Reference page 910

Hard processor system
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cv_5v4
2016.10.28
31
30
15
14
onfi_device_no_of_blocks_per_lun_l Fields
Bit
15:0
value
onfi_device_no_of_blocks_per_lun_u
Upper bits of number of blocks per LUN present in the ONFI complaint device.
Module Instance
nandregs
Offset:
0x3E0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
onfi_device_no_of_blocks_per_lun_u Fields
Bit
15:0
value
NAND Flash Controller
Send Feedback
29
28
27
26
13
12
11
10
Name
Indicates the lower bits of number of blocks per LUN
present in the ONFI complaint device.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Name
Indicates the upper bits of number of blocks per LUN
present in the ONFI complaint device.
onfi_device_no_of_blocks_per_lun_u
Bit Fields
25
24
23
22
Reserved
9
8
7
6
value
RO 0x0
Description
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
value
RO 0x0
Description
21
20
19
18
5
4
3
2
Access
Register Address
0xFFB803E0
21
20
19
18
5
4
3
2
Access
13-89
17
16
1
0
Reset
RO
0x0
17
16
1
0
Reset
RO
0x0
Altera Corporation

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