Altera cyclone V Technical Reference page 90

cv_5v4
2016.10.28
emac1clk
Contains settings that control clock emac1_clk generated from the C1 output of the Peripheral PLL. Only
reset by a cold reset.
Module Instance
clkmgr
Offset:
0x8C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
emac1clk Fields
Bit
8:0
cnt
perqspiclk
Contains settings that control clock periph_qspi_clk generated from the C2 output of the Peripheral PLL.
Only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x90
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Clock Manager
Send Feedback
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
0xFFD04000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
emac1clk
Register Address
0xFFD0408C
21 20 19 18
5 4 3 2
cnt
RW 0x1
Access
Register Address
0xFFD04090
2-53
17 16
1 0
Reset
RW 0x1
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