cv_5v4
2016.10.28
Bits
11 FIFO Underrun/Overrun Error (FRUN)
10 Data Starvation by Host Timeout (HTO)
9
Data Read Timeout (DRTO)/Boot Data Start
†
(BDS)
SD/MMC Controller
Send Feedback
Interrupt
†
†
Interrupt Controller Unit
Description
Host tried to push data when FIFO was full, or
host tried to read data when FIFO was empty.
Typically this should not happen, except due to
†
error in software.
Card unit never pushes data into FIFO when
FIFO is full, and pop data when FIFO is empty.
If IDMAC (Internal Direct Memory Access
Controller) is enabled, FIFO underrun/overrun
can occur due to a programming error on
MSIZE and watermark values in FIFOTH
register; for more information, refer to Internal
Direct Memory Access Controller (IDMAC)
section in the "Synopsys DesignWare Cores
Mobile Storage Host Databook".
To avoid data loss, card clock out (
stopped if FIFO is empty when writing to card,
or FIFO is full when reading from card.
Whenever card clock is stopped to avoid data
loss, data-starvation timeout counter is started
with data-timeout value. This interrupt is set if
host does not fill data into FIFO during write to
card, or does not read from FIFO during read
from card before timeout period.
Even after timeout, card clock stays in stopped
state, with CIU state machines waiting. It is
responsibility of host to push or pop data into
FIFO upon interrupt, which automatically
restarts
and card state machines.
cclk_out
Even if host wants to send stop/abort command,
it still must ensure to push or pop FIFO so that
clock starts in order for stop/abort command to
send on cmd signal along with data that is sent
†
or received on data line.
• In Normal functioning mode: Data read
timeout (DRTO) Data timeout occurred.
Data Transfer Over (DTO) also set if data
†
timeout occurs.
• In Boot Mode: Boot Data Start (BDS) When
set, indicates that SD/MMC controller has
started to receive boot data from the card. A
write to this register with a value of 1 clears
†
this interrupt.
14-9
†
†
) is
cclk_out
†
†
Altera Corporation