Altera cyclone V Technical Reference page 877

13-56
re_2_we
tcwaw_and_addr_2_data Fields
Bit
13:8
tcwaw
5:0
addr_2_data
re_2_we
Timing parameter between re high to we low (Trhw)
Module Instance
nandregs
Offset:
0x120
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
re_2_we Fields
Bit
5:0
value
Altera Corporation
Name
Signifies the number of controller clocks that should
be introduced between the command cycle of a
random data input command to the address cycle of
the random data input command.
Signifies the number of bus interface nand_mp_clk
clocks that should be introduced between address
latch enable going low to write enable going low. The
number of clocks is the function of device parameter
Tadl and controller clock frequency.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Signifies the number of bus interface nand_mp_clk
clocks that should be introduced between read enable
going high to write enable going low. The number of
clocks is the function of device parameter Trhw and
controller clock frequency.
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Access
Register Address
0xFFB80120
21 20 19 18
5 4 3 2
value
RW 0x32
Access
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x14
RW 0x32
17 16
1 0
Reset
RW 0x32
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