Functional Description Of The Usb Otg Controller - Altera cyclone V Technical Reference

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Functional Description of the USB OTG Controller

Functional Description of the USB OTG Controller
USB OTG Controller Block Description
Figure 18-2: USB OTG Controller Block Description
Details about each of the units that comprise the USB OTG controller are shown below.
Master Interface
The master interface includes a built-in DMA controller. The DMA controller moves data between
external memory and the media access controller (MAC).
Properties of the master interface are controlled through the USB L3 Master HPROT Register (
in the system manager. These bits provide access information to the L3 interconnect, including whether or
not transactions are cacheable, bufferable, or privileged.
Note: Bits in the
an inactive state.
Altera Corporation
USB OTG
Master Interface
Controller
SPRAM
register can be updated only when the master interface is guaranteed to be in
l3master
L3 Interconnect
Slave Interface
Application Interface Unit
Packet FIFO Controller
Media Access Controller
Wakeup and PHY Controller
PHY Interface
ULPI PHY Interface
External USB Transceiver
cv_5v4
2016.10.28
)
l3master
USB 2.0 OTG Controller
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