Quad Spi Flash Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Exiting XIP Mode
To exit XIP mode, perform the following steps:
1. Disable the direct access controller and indirect access controller to ensure no new read or write
accesses are sent to the flash device.
2. Restore the mode bits to the values before entering XIP mode, depending on the flash device and
manufacturer.
3. Set the
enterxipnextrd
The flash device must receive a read instruction before it can disable its internal XIP mode state.
Thus, XIP mode internally stays active until the next read instruction is serviced. Ensure that XIP
mode is disabled before the end of any read sequence.
XIP Mode at Power on Reset
Some flash devices can be XIP-enabled as a nonvolatile configuration setting, allowing the flash device to
enter XIP mode at power-on reset (POR) without software intervention. Software cannot discover the XIP
state at POR through flash status register reads because an XIP-enabled flash device can only be accessed
through the XIP read operation. If you known the device will enter XIP mode at POR, have your initial
boot software configure the
If you do not know in advance whether or not the device will enter XIP mode at POR, have your initial
boot software issue an XIP mode exit command through the
the "Entering XIP Mode" section. Software must be aware of the mode bit requirements of the device,
because XIP mode entry and exit varies by device.
Related Information
Entering XIP Mode

Quad SPI Flash Controller Address Map and Register Definitions

The address map and register definitions for the Quad SPI Flash Controller consist of the following
regions:
• QSPI Flash Controller Module Registers
• QSPI Flash Module Data
QSPI Flash Controller Module Registers Address Map
Registers in the QSPI Flash Controller module accessible via its APB slave
QSPI Flash Module Data (AHB Slave) Address Map
This address space is allocated for QSPI direct, indirect, and SPI legacy mode accesses. For more
information, please refer to the Quad SPI Flash Controller chapter in the Hard Processor System Technical
Reference Manual.
Related Information
• QSPI Flash Controller Module Registers Summary
• QSPI Flash Module Data (AHB Slave) Summary
Introduction to the Hard Processor System
•
Quad SPI Flash Controller
Send Feedback
bit of the register to 0.
cfg
register and set the
modebit
on page 15-18
bit of the
enterxipimm
register, then follow the steps in
flashcmd
on page 15-20
on page 15-61
on page 1-1
15-19
Exiting XIP Mode
register to 1.
cfg
Altera Corporation