Altera cyclone V Technical Reference page 683

cv_5v4
2016.10.28
31 30
force Reserved
RW 0x0
15 14
Reserved
vid6rd Fields
Bit
31
force
27:16
mid
13:12
page
8:4
user
vid6wr
The Write AXI Master Mapping Register contains the USER, ADDR page, and ID signals mapping values
for particular transaction with 12-bit ID which locks the fixed 3-bit virtual ID.
Module Instance
acpidmap
Offset:
0x24
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Cortex-A9 Microprocessor Unit Subsystem
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29 28 27 26
13 12 11 10
page Reserved
RW 0x0
Name
Set to 1 to force the mapping between the 12-bit ID
and 3-bit virtual ID N. Set to 0 to allow the 3-bit ID N
to be dynamically allocated.
The 12-bit ID of the master to remap to 3-bit virtual
ID N, where N is the 3-bit ID to use.
ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory
region.
This value is propagated to SCU as ARUSERS.
0xFF707000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
RW 0x0
9 8 7 6
user
RW 0x0
Description
Base Address
21 20 19 18
mid
5 4 3 2
Reserved
Access
Register Address
0xFF707024
9-47
vid6wr
17 16
1 0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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