Features Of The Dma Controller - Altera cyclone V Technical Reference

2016.10.28
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This chapter describes the direct memory access controller (DMAC) contained in the hard processor
system (HPS). The DMAC transfers data between memory and peripherals and other memory locations in
the system. The DMA controller is an instance of the ARM Corelink DMA Controller (DMA-330).
Related Information
ARM Information Center
For more information about ARM's DMA-330 controller, refer to the CoreLink DMA Controller DMA-330
Revision: r1p2 Technical Reference Manual on the ARM Infocenter website.

Features of the DMA Controller

The HPS provides one DMAC to handle the data transfer between memory-mapped peripherals and
memories, off-loading this work from the microprocessor unit (MPU) subsystem.
The DMAC supports multiple transfer types:
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
The DMAC supports up to:
• Eight logical channels for different levels of service requirements
• 31 peripheral handshake interfaces for peripheral hardware flow control
The DMAC provides:
• An instruction processing block that enables it to process program code that controls a DMA transfer
• An ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI)
master interface unit to fetch the program code from system memory into its instruction cache
Note: The AXI master interface also performs DMA data transfer. The DMA instruction execution
engine executes the program code from its instruction cache and schedules read or write AXI
instructions through the respective instruction queues.
• A multi-FIFO (MFIFO) data buffer that stores data that it reads, or writes, during a DMA transfer
• 11 interrupt outputs to enable efficient communication of events to the MPU subsystem
Note: The peripheral request interfaces support the connection of DMA-capable peripherals to enable
memory-to-peripheral and peripheral-to-memory transfers to occur, without intervention from
the processor.
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