Altera cyclone V Technical Reference page 928

cv_5v4
2016.10.28
Bit
6
load_comp
5
erase_fail
4
program_fail
3
time_out
2
dma_cmd_comp
1
RSVD
0
ecc_uncor_err
page_cnt2
Decrementing page count bank 2
Module Instance
nandregs
Offset:
0x4D0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
Send Feedback
Name
Device finished the last issued load command.
Erase failure occurred in the device on issuance of a
erase command. err_block_addr and err_page_addr
contain the block address and page address that failed
erase operation.
Program failure occurred in the device on issuance of
a program command. err_block_addr and err_page_
addr contain the block address and page address that
failed program operation.
Watchdog timer has triggered in the controller due to
one of the reasons like device not responding or
controller state machine did not get back to idle
A data DMA command has completed on this bank.
RSVD
If set, Controller will interrupt processor when Ecc
logic detects uncorrectable error.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
page_cnt2
Access
Register Address
0xFFB804D0
21 20 19 18
5 4 3 2
value
RO 0x0
13-107
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
R 0x0
RW 0x0
17 16
1 0
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