Altera cyclone V Technical Reference page 175

Hard processor system
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4-32
gpio_inttype_level
Bit
8
ncp
7
prd
6
pre
5
prr
4
ccd
Altera Corporation
Name
Controls whether the level of nCONFIG Pin or an
edge on nCONFIG Pin generates an interrupt.
Value
0x0
0x1
Controls whether the level of PR_DONE or an edge
on PR_DONE generates an interrupt.
Value
0x0
0x1
Controls whether the level of PR_ERROR or an edge
on PR_ERROR generates an interrupt.
Value
0x0
0x1
Controls whether the level of PR_READY or an edge
on PR_READY generates an interrupt.
Value
0x0
0x1
Controls whether the level of CVP_CONF_DONE or
an edge on CVP_CONF_DONE generates an
interrupt.
Value
0x0
0x1
Description
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
Description
Level-sensitive
Edge-sensitive
cv_5v4
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
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