Local Memory Buffer - Altera cyclone V Technical Reference

13-6

Local Memory Buffer

The sizes of the main and spare areas, and the number of blocks in a page, depend on the specific NAND
device connected to the NAND flash controller. Therefore, the device-dependent registers,
device_main_area_size
match the characteristics of the device.
If your software does not perform the discovery and initialization sequence, the software must include an
alternative method to determine the correct value of the device-dependent registers. The HPS boot ROM
code enables discovery and initialization by default (that is,
Local Memory Buffer
The NAND flash controller has three local SRAM memory buffers. Of the three, only the read and write
clocks are asynchronous.
• ECC buffer—Operates at the core clock, it enables the simultaneous process between sending out the
data to the host and receiving data from the device to achieve a line rate operation.
• Write FIFO—The write port operates at
large enough to pre-allocate all the read data associated with the number of the outstanding read
requests that it could issue to the hosts. Up to 8 outstanding read requests are supported, with a
maximum burst size of 64 bytes. Therefore, the write FIFO buffer is a 128 × 32-bit memory (512 total
bytes).
• Read FIFO—The read port operates at
number of outstanding read requests that it could receive from the host, it only requires a buffer size
that is just enough to sustain the streaming from the device memory to the system bus. Therefore, the
read FIFO buffer is a 32 × 32-bit memory (128 total bytes). Since the size of the read FIFO is relatively
small for SRAM implementation, it can be implemented using flops.
Clocks
To minimize the number of clocks, Clock Manager outputs software managed enables to the USB, SPI
Masters, QSPI and NAND peripherals. The software enable for NAND is
ENABLE by default. Also, in Boot Mode,
is cleared for security.
Table 13-4: Clock Inputs to NAND Flash Controller
Clock Signal
nand_x_clk
nand_clk
The frequency of
Clock Generation
The clock manager sends the top level clock from the HPS.
The clock manager sends the 200 MHz clock,
becomes the NAND reference clock called
for input and output. Since the NAND places a 200 MHz limit on the clock, each of these four generated
clocks are 50 MHz and called
Altera Corporation
,
device_spare_area_size
nand_clk_en
Clock for master and slave interfaces and the ECC sector buffer.
Clock for the NAND flash controller.
is four times the frequency of
nand_x_clk
.
nand_clk
, and
pages_per_block
bootstrap_inhibit_init = 0)
and the read port operates at
aclk
and the write port operates at
aclk
is active to ensure that all clocks are active if RAM
Description
nand_clk
, to the NAND Flash Controller. This clock
l4_mp_clk
. The
nand_mp_clk nand_mp_clk
, must be programmed to
.
. The buffer must be
clk
. Regardless of the
clk
and is set to
nand_clk_en
.
is divided by four and is used
NAND Flash Controller
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cv_5v4
2016.10.28