System Manager Block Diagram And System Integration - Altera cyclone V Technical Reference

5-2

System Manager Block Diagram and System Integration

System Manager Block Diagram and System Integration
The system manager connects to the level 4 (L4) bus through a slave interface. The CSRs connect to signals
in the FPGA and other HPS modules.
Figure 5-1: System Manager Block Diagram
HPS BSEL pins
Altera Corporation
System Manager
Watchdog
Debug Pause
Register
Slave
Interface
CSRs
Pause
L4 Watchdog Timers
Debug Status
MPU
Logic with
Parity Injection
Parity RAM
ECC & Parity
Generic Interrupt
Interrupts
Controller
Memory-Mapped
Control Signals
Other Modules
ECC Control and
Status Signals
Modules with
ECC RAM
FPGA JTAG Control
FPGA
Control
FPGA
Block
Fabric
cv_5v4
2016.10.28
System Manager
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