Altera cyclone V Technical Reference page 235

Hard processor system
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cv_5v4
2016.10.28
Bit
5
dllrst
4
slew
3
wkpullup
2
tristate
1
bushold
0
cfg
System Manager
Send Feedback
Name
Controls DLL (Delay-Locked Loop) reset.
Value
0x0
0x1
Controls IO slew-rate
Value
0x0
0x1
Controls weak pullup resistor
Value
0x0
0x1
Controls IO tri-state
Value
0x0
0x1
Controls bus hold circuit
Value
0x0
0x1
Controls IO configuration
Value
0x0
0x1
Description
Description
No reset or clock gating.
Resets registers in the DLL and gates off DLL
clock.
Description
Slew-rate forced to slow.
Slew-rate controlled by IO configuration.
Description
Weak pullup resistor enabled.
Weak pullup resistor enable controlled by IO
configuration.
Description
IO tri-state enabled.
IO tri-state controlled by IO configuration.
Description
Disable bus hold circuit.
Bus hold circuit controlled by IO configura‐
tion.
Description
Disable IO configuration (forced to a safe
value).
Enables IO configuration as previously
configured by software using the Scan
Manager.
5-41
hioctrl
Access
Reset
RW
0x1
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Altera Corporation

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