Altera cyclone V Technical Reference page 597

cv_5v4
2016.10.28
comp_id_3 Fields
Bit
7:0
preamble
Slave Register Group Register Descriptions
Registers associated with slave interfaces.
Offset:
0x42000
32-bit Slave Register Descriptions
Registers associated with the 32-bit AXI slave interface. These registers are only active when the
FPGA2HPS AXI Bridge is configured with a 32-bit FPGA AXI slave interface.
Offset:
0x0
fn_mod2
on page 8-15
Controls bypass merge of upsizing/downsizing.
fn_mod on page 8-16
Sets the block issuing capability to multiple or single outstanding transactions.
fn_mod2
Controls bypass merge of upsizing/downsizing.
Module Instance
fpga2hpsregs
Offset:
0x42024
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
HPS-FPGA Bridges
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Name
Preamble
0xFF600000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Slave Register Group Register Descriptions
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Access
Register Address
0xFF642024
21 20 19 18
5 4 3 2
8-15
Reset
RO 0xB1
17 16
1 0
bypass_
merge
RW 0x0
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