Altera cyclone V Technical Reference page 619

cv_5v4
2016.10.28
L3 Slave Register Group
Register
fn_mod on page 8-50
ID Register Group Register Descriptions
Contains registers that identify the ARM NIC-301 IP Core.
Offset:
0x1000
periph_id_4
JEP106 continuation code
periph_id_0
Peripheral ID0
periph_id_1
Peripheral ID1
periph_id_2
Peripheral ID2
periph_id_3
Peripheral ID3
comp_id_0
Component ID0
comp_id_1
Component ID1
comp_id_2
Component ID2
comp_id_3
Component ID3
periph_id_4
JEP106 continuation code
Module Instance
lwhps2fpgaregs
Offset:
0x1FD0
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
HPS-FPGA Bridges
Send Feedback
Offset Width Acces
0x45108
on page 8-37
on page 8-38
on page 8-38
on page 8-39
on page 8-40
on page 8-41
on page 8-41
on page 8-42
on page 8-42
0xFF400000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
ID Register Group Register Descriptions
Reset Value
s
32 RW 0x0
Base Address
Description
Issuing Functionality Modification
Register
Register Address
0xFF401FD0
8-37
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