Document Revision History - Altera cyclone V Technical Reference

8-54

Document Revision History

FPGA Slaves Accessed Via Lightweight HPS2FPGA AXI Bridge (lwfpgaslaves) Address Map
•
page 8-51
This address space is allocated for FPGA-configured slaves driven by the lightweight HPS-to-FPGA bridge
master. Address assignment within this space is user-defined. For more information about Lightweight
HPS-to-FPGA bridges, refer to the HPS-FPGA Bridges chapter of the Hard Processor System Technical
Reference Manual.
HPS Peripheral Region Address Map
•
Lists the base addresses of all modules
Cyclone V Address Map and Register Definitions
•
Web-based address map and register definitions
Document Revision History
Table 8-16: Document Revision History
Date
October 2016
November 2015
May 2015
December 2014
June 2014
February 2014
December 2013
November 2012
January 2012
Altera Corporation
Version
2016.10.28 Maintenance release
2015.11.02 Maintenance release
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.06.30 Added address maps and register definitions
2014.02.28 Maintenance release
2013.12.30 Maintenance release
1.1 Described GPV
1.0 Initial release
on page 1-17
Changes
cv_5v4
2016.10.28
on
HPS-FPGA Bridges
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